Aspect-based ABV for SystemC transaction level models
ABSTRACT Transaction level modeling (TLM) is increasingly being adopted to describe hardware designs at high abstraction levels. This paper proposes a framework that targets the assertion-based verification (ABV) of SystemC transaction level models during simulation. Aspect-oriented (AO) mechanisms are exploited to write temporal properties that fit TLM requirements. No modifications are needed in the design's SystemC code. Functional as well as performance properties are addressed. We demonstrate the effectiveness of our approach on TLM 2.0 standard compliant models.
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ABSTRACT: As embedded systems incorporate more and more amounts of IP and embedded software the functional and nonfunctional verification task is one of the key bottlenecks in the design process. Despite proprietary design and verification languages such as IEEE-1800 SystemVerilog and IEEE-1647 e offer CDV functionalities neither SystemC or the SCV addon library contain these features. Moreover, as programming languages and verification paradigms of the hardware and software domain continue to converge the verification techniques and methodologies need to take account of that, e.g. by adaption of the aspect-oriented programming scheme. In this paper we describe an approach for enhancing the functional coverage collection in the SystemC ecosystem by means of aspects, allowing cross-cutting the concern of CDV verification in stand-alone aspects, increasing the overall verification productivity.
Conference Paper: A TLM2.0 assertion library with centralized monitoring approach[Show abstract] [Hide abstract]
ABSTRACT: In recent years, design verification gained importance as a result of ever growing complexity and increasing cost of malfunctioning hardware. This resulted in various approaches for verification. On the other hand, higher abstraction levels introduced to help designer cope with the complexity of the designs. Different or specialized verification methods are needed for each abstraction level. Assertion based verification (ABV) is a well known method of verification that could be used for higher abstraction levels such as transaction level modeling (TLM) as well as older ones like register transfer level (RTL). Designers can define assertions by specific languages or use predefined libraries to verify their designs. In this paper, a library of assertions is presented that could be easily used to verify TLM2.0 designs. They introduce some new capabilities such as timing verification and cross channel verification which has not been presented before.Design & Test Symposium (EWDTS), 2010 East-West; 10/2010
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ABSTRACT: paper presents the design of a SystemC transaction level modelling wrapping library that can be used for the assertion of system properties, protocol compliance, or fault injection. The library uses C++ virtual table hooks as a dynamic binary instrumentation technique to inline wrappers in the TLM2 transaction path. This technique can be applied after the elaboration phase and needs neither source code modifications nor recompilation of the top level SystemC modules. The proposed technique has been successfully applied to the robustness verification of the on-board boot software of the Instrument Control Unit of the Solar Orbiter's Energetic Particle Detector.Modelling and Simulation in Engineering 09/2014; DOI:10.1155/2014/105051