A synchronous FPGA design of a bilateral filter for image processing
ABSTRACT In this paper a new FPGA design concept of a bilateral filter for image processing is presented. With the aid of this design the bilateral filter can be realized as a highly parallelized pipeline structure with very good utilization of dedicated resources. The innovation of the design concept lies in sorting the input data into groups in a manner that kernel based processing is possible. Another feature of the kernel based design concept is the increase of the clock to the quadruple of the pixel clock in the filter architecture. The sorting of the pixels and the quadruplication of the pixel clock are the key to the synchronous FPGA design using a parallelized pipeline architecture. The synchronicity of the design assures constant output delay which can be computed after the hardware specification is known. For acceleration of the design concept the separability and symmetry of the geometric filter component is utilized, also reducing the complexity of the design. Combined with parallel pipeline design a significant decrease of resource consumption can also be achieved. Thus the presented design can easily be implemented on a common medium sized FPGA.
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ABSTRACT: In this work, a novel way to adjust a bilateral filter is presented. The bilateral filter is a combination of domain and range filtering. The domain filter acts as a low-pass filter. The range filter stands for the nonlinear component and plays an important part in edge preserving. Both filtering components can be adjusted by according parameters. Pursuant to our experience and achieved results in terms of the image quality it is more effective to readjust the range filter to the noise level than to cope with the fine tuning of the spatial filter. In this work, we show how the adjustment parameter for the nonlinear range component can be derived from the standard deviation of noise, which allows automatic noise-adaptive adjustment of the filter.01/2011; DOI:10.1109/IECON.2011.6120053
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ABSTRACT: This paper presents an efficient and scalable design for histogram-based bilateral filtering (BF) and joint BF (JBF) by memory reduction methods and architecture design techniques to solve the problems of high memory cost, high computational complexity, high bandwidth, and large range table. The presented memory reduction methods exploit the progressive computing characteristics to reduce the memory cost to 0.003%-0.020%, as compared with the original approach. Furthermore, the architecture design techniques adopt range domain parallelism and take advantage of the computing order and the numerical properties to solve the complexity, bandwidth, and range-table problems. The example design with a 90-nm complementary metal-oxide-semiconductor process can deliver the throughput to 124 Mpixels/s with 356-K gate counts and 23-KB on-chip memory.IEEE Transactions on Image Processing 11/2011; 20:3231-3241. DOI:10.1109/TIP.2011.2159226 · 3.63 Impact Factor
Conference Paper: Memory optimization of bilateral filter and its hardware implementation[Show abstract] [Hide abstract]
ABSTRACT: As a method for edge-preserving or noise-reducing, a bilateral filter is widely used. However, because every pixel in a filtering window needs a separate Look-Up Table (LUT) for the parallel processing, its hardware implementation is still bulky. In this paper, we propose Similar Weight Grouping (SWG) which maps multiple indexes with a similar value onto a single index and Zero Value Suppression (ZVS) which removes indexes with a value of almost zero to reduce a size of the LUT. By our scheme, a total size of LUT is reduced by approximately 95% while maintaining its performance. Finally, it is implemented using 7.7 KB on-chip memory and 93.1 Kgates with 65 nm process.2014 International Symposium on Consumer Electronics (ICSE); 06/2014