A VLSI implementation of a 3Gb/s LVDS transceiver in CMOS technology
ABSTRACT In this paper is presented the implementation of a transceiver for 3Gb/s operation, fully compatible with low-voltage differential signaling (LVDS) and Gen2i, Gen2m serial ATA standards. Due to the differential transmission technique and the low voltage swing, LVDS allows both high transmission speeds and low power consumption at the same time. The proposed transceiver is composed by a transmitter (TX) and a receiver (RX) circuits. The TX circuit provides a dc level independent over process, temperature, and supply voltage variations, by using a closed-loop control circuit and an internal voltage reference. The RX circuit is represented by a simple comparator based on the Schmitt trigger circuit. Both transmitter and receiver circuits show a dc current consumption of 20mA from 3.3V supply voltage. The simulations performed in a 0.18Â¿m CMOS technology confirm the theoretical results.
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ABSTRACT: The switch element (SE) is a 622Mb/s, 8×8 shared-buffer ATM switch LSI for backbone LAN and WAN applications. The SE has 5 Gbps bandwidth, supporting 5 QoS classes delay priority and link-by-link multicast. Up to a 32×32 switch with 20 Gbps bandwidth can be configured using multiple SEs and distributor/arbiter (DA) LSIsSolid-State Circuits Conference, 1996. Digest of Technical Papers. 42nd ISSCC., 1996 IEEE International; 03/1996