Conference Proceeding

Low-power and robust six-FinFET memory cell using selective gate-drain/source overlap engineering

Dept. of Electr. & Comput. Eng., Univ. of Wisconsin-Madison, Madison, WI, USA
01/2010; pp.244 - 247 In proceeding of: Integrated Circuits, ISIC '09. Proceedings of the 2009 12th International Symposium on
Source: IEEE Xplore

ABSTRACT A new FinFET memory circuit technique based on gate-drain/source overlap engineering is proposed in this paper. The read stability of the proposed SRAM circuit is enhanced by 53% and the leakage power is reduced by 48% as compared to a minimum sized low-threshold-voltage FinFET SRAM cell in a 32 nm FinFET technology. Furthermore, the layout area of the proposed SRAM circuit is reduced by 17% as compared to a FinFET SRAM circuit with longer-channel access transistors. The proposed technique based on gate-drain/source overlap engineering is easier to be implemented with fewer processing steps as compared to the previously published data stability enhancement techniques based on independent-gate bias and gate work-function engineering in FinFET memory circuits.

0 0
 · 
0 Bookmarks
 · 
18 Views
Data provided are for informational purposes only. Although carefully collected, accuracy cannot be guaranteed. The impact factor represents a rough estimation of the journal's impact factor and does not reflect the actual current impact factor. Publisher conditions are provided by RoMEO. Differing provisions from the publisher's actual policy or licence agreement may be applicable.

Keywords

32 nm FinFET technology
 
FinFET memory circuits
 
gate work-function engineering
 
gate-drain/source overlap engineering
 
independent-gate bias
 
minimum sized low-threshold-voltage FinFET SRAM cell
 
published data stability enhancement techniques