Article
A DigitallyCalibrated PhaseLocked Loop With Supply Sensitivity Suppression
Grad. Inst. of Electron. Eng. & Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (Impact Factor: 1.22). 05/2011; DOI: 10.1109/TVLSI.2009.2039359 Source: IEEE Xplore

Conference Paper: Design and analysis of CMOS ring oscillator using 45 nm technology
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ABSTRACT: This paper represents the design and analysis of ring oscillator using cadence virtuoso tool in 45 nm technology. Ring oscillator consists of odd number of stages with feedback circuit which forms a closed loop in which each stage output depends on the previous stage. In this paper, nine stage ring oscillator have been designed with a capacitor of 1 fF at each stage and simulated for various parameters such as delay, noise, jitter and power consumption. Power consumption, jitter, noise have been reduced in nine stage ring oscillator. Periodic steady state response of ring oscillator is also observed. Power consumption is reduced by 18.9%.Advance Computing Conference (IACC), 2013 IEEE 3rd International; 01/2013  [Show abstract] [Hide abstract]
ABSTRACT: A phaselocked loop (PLL) is proposed for lowvoltage applications. A new charge pump (CP) circuit, using gate switches affords low leakage current and high speed operation. A lowvoltage voltagecontrolled oscillator (LVVCO) composed of 4stage delay cells and a lowvoltage segmented current mirror (LVSCM) achieves low voltagecontrolled oscillator gain ( K <sub>VCO</sub>), a wide tuning range, and good linearity. A LVSCM generates more current with small area by switching the body rather than the gate. The PLL is implemented in standard 90nm CMOS with regular VT (RVT) devices. Its output jitter is 2.22 ps (rms), which is less than 0.5% of the output period. The phase noise is  87 dBc/Hz at 1MHz offset from a 2.24GHz center frequency. Total power dissipation at 2.24GHz output frequency, and with 0.5V power supply is 2.08 mW (excluding the buffers). The core area is 0.074 mm<sup>2</sup>.Circuits and Systems I: Regular Papers, IEEE Transactions on 06/2011; · 2.24 Impact Factor
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