Article

# A Digitally-Calibrated Phase-Locked Loop With Supply Sensitivity Suppression

Grad. Inst. of Electron. Eng. & Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

IEEE Transactions on Very Large Scale Integration (VLSI) Systems (Impact Factor: 1.14). 05/2011; DOI: 10.1109/TVLSI.2009.2039359 Source: IEEE Xplore

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**ABSTRACT:**A phase-locked loop (PLL) is proposed for low-voltage applications. A new charge pump (CP) circuit, using gate switches affords low leakage current and high speed operation. A low-voltage voltage-controlled oscillator (LV-VCO) composed of 4-stage delay cells and a low-voltage segmented current mirror (LV-SCM) achieves low voltage-controlled oscillator gain ( K <sub>VCO</sub>), a wide tuning range, and good linearity. A LV-SCM generates more current with small area by switching the body rather than the gate. The PLL is implemented in standard 90-nm CMOS with regular VT (RVT) devices. Its output jitter is 2.22 ps (rms), which is less than 0.5% of the output period. The phase noise is - 87 dBc/Hz at 1-MHz offset from a 2.24-GHz center frequency. Total power dissipation at 2.24-GHz output frequency, and with 0.5-V power supply is 2.08 mW (excluding the buffers). The core area is 0.074 mm<sup>2</sup>.Circuits and Systems I: Regular Papers, IEEE Transactions on 06/2011; · 2.30 Impact Factor -
##### Conference Paper: Design and analysis of CMOS ring oscillator using 45 nm technology

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**ABSTRACT:**This paper represents the design and analysis of ring oscillator using cadence virtuoso tool in 45 nm technology. Ring oscillator consists of odd number of stages with feedback circuit which forms a closed loop in which each stage output depends on the previous stage. In this paper, nine stage ring oscillator have been designed with a capacitor of 1 fF at each stage and simulated for various parameters such as delay, noise, jitter and power consumption. Power consumption, jitter, noise have been reduced in nine stage ring oscillator. Periodic steady state response of ring oscillator is also observed. Power consumption is reduced by 18.9%.Advance Computing Conference (IACC), 2013 IEEE 3rd International; 01/2013 - [Show abstract] [Hide abstract]

**ABSTRACT:**This paper presents a source-follower-delay-cell, multiloop ring oscillator that provides power-supply isolation. The main contributions of this work are a source-follower-based delay cell with a multiloop ring structure achieving improved supply rejection, a design-oriented analysis of the proposed structure to facilitate its use, and a layout technique allowing straightforward mask design for the multiloop oscillator. The oscillator also features differential control voltages to allow rejection of common-mode control and supply noise. The oscillator was fabricated in a UMC 90-nm CMOS pure logic process with no analog components (regular VT), and the minimum measured incremental supply sensitivity is 0.003 [%-change fosc/%-change VDD], which is more than 20 dB better than that of a conventional CMOS-delay-cell quadrature oscillator fabricated on the same test chip. The oscillator's measured tuning range is 0.63-8.1 GHz. Over the tuning range, the phase noise varies from - 106 to - 88 dBc/Hz at 10-MHz offset, and the power consumption ranges from 7 to 26 mW from a 1-V supply. The measured mean quadrature accuracy performance is within -1.5° to +2.25° error including board parasitics without any trimming/tuning across the oscillator's frequency range.IEEE Journal of Solid-State Circuits 09/2012; 47(9):2033-2048. · 3.11 Impact Factor

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