592IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 19, NO. 4, APRIL 2011
A Digitally-Calibrated Phase-Locked Loop With
Supply Sensitivity Suppression
Shih-Yuan Kao and Shen-Iuan Liu, Fellow, IEEE
Abstract—A digitally-calibrated technique to suppress the
supply voltage sensitivity of a phase-locked loop (PLL) is pre-
sented. The voltage-controlled ring oscillator with an additional
opposite-supply-sensitivity pair is digitally calibrated to sup-
press the supply voltage sensitivity. The circuit is fabricated in a
0.18- m CMOStechnology and the core area occupies 0.235mm?.
The total power consumption is 16.2 mW for a supply voltage of
1.8 V and an operating frequency of 1.5 GHz. For a 100 mV??,
110 kHz sinusoidal waveform noise applied to the supply, the
measured rms jitters without and with calibration are 16.5 and
9.7 ps, respectively, while this PLL works at 1.5 GHz. This PLL
achieves the rms jitter improvement by a factor of 41.2% under
the proposed digitally-calibrated technique.
Index Terms—Band-pass characteristic, digital calibration,
phased-locked loop (PLL), supply voltage sensitivity.
The performance of PLLs has been strictly specified in phase
noise, timing jitter, and reference spur level. In a PLL, the
voltage-controlled oscillator (VCO) is sensitive to process
variations, supply voltage perturbation, and environmental
temperature. In a complex mixed-signal system, when the large
switching transients of the digital circuits occur, the inductive
supply noise (Ldi/dt) will interfere with the noise-sensitive
analog circuits such as VCOs and charge pumps. While the
VCOs suffer from the transient power supply noise, the timing
jitter will degrade. It would be much larger than the jitter
caused by the inherent device electronic noise of the oscillators
such as 1/f noise and thermal noise , . Traditionally, the
passive decoupling capacitance connected between the supply
and ground has been effectively used to suppress power supply
noise. However, it inevitably occupies the additional area in the
Several methods are presented to reduce the power supply
noise impacts on PLLs. In –, the voltage regulator is
adopted to mitigate the power supply noise but the available
voltage headroom is reduced and the bandwidth of the regulator
must be wider than the PLL bandwidth for better supply noise
rejection. The excessive power consumption is also needed. In
HASE-LOCKED LOOPS (PLLs) have been widely used
in modern wireline and wireless communication systems.
Manuscript received August 29, 2009; revisedDecember 01, 2009. First pub-
lished January 29, 2010; current version published March 23, 2011. This work
was supported in part by National Chip Implementation Center (CIC) for chip
fabrication and NSC, Taiwan.
The authors are with the Graduate Institute of Electronics Engineering and
Department of Electrical Engineering, National Taiwan University, Taipei
10617, Taiwan (e-mail: firstname.lastname@example.org).
Digital Object Identifier 10.1109/TVLSI.2009.2039359
–, although the compensation technique with reduced
supply voltage sensitivity is used on the VCO and output clock
buffer, it is actually hard to achieve accurate compensation
because of process variations. In , an adaptive supply com-
pensation technique is employed to reduce the supply voltage
sensitivity even if the process variations exist. However, its
calibration mechanism needs to close and break the PLL alter-
natively and it leads into the long calibration time. In –,
the passive and active decoupling techniques are used but a
large area for passive and active decoupling capacitance is
tally-calibratedopposite-supply-sensitivitypair is presented.To
save the power consumption, the digital calibration circuit is
turned off once the calibration is completed. To reduce the cal-
ibration time, the successive approximation register method is
adopted. This paper is organized as follows. Section II intro-
duces the analysis and suppression technique for supply voltage
sensitivity. The circuit description is presented in Section III.
The experimental results are given in Section IV. Finally, the
conclusions are given in Section V.
II. ANALYSIS AND SUPPRESSION FOR SUPPLY
A. Supply Voltage Sensitivity Analysis
In order to analysis the supply disturbance on the PLL, the
supply noise model of the PLL with a first-order passive loop
filter is shown in Fig. 1. For simplicity, only the supply noise
contribution is considered and the VCO is modeled with two
controlling voltages. One is the control voltage from the loop
filter and the gain is denoted as
voltage and the gain is denoted as
to the output phaseas
. The other is the supply
. Once the fluctuation
noise results in timing jitter increased and the effect is propor-
. The closed-loop transfer function from supply
toin Fig. 1 is derived as
is the VCO’s output phase. The additional phase
1063-8210/$26.00 © 2010 IEEE
KAO AND LIU: DIGITALLY-CALIBRATED PLL WITH SUPPLY SENSITIVITY SUPPRESSION593
Fig. 1. Supply noise model of the PLL.
PARAMETERS FOR THIS PLL
From (2), it exhibits a band-pass characteristic. It is rewritten in
a standard second-order form as
is thecharge-pump currentandis thedivision ratio.
Assume that the supply noise spectrum
Gaussian noise. The contributed power spectrum on the PLL
output is denoted as
sign parameters in Table I, the simulated supply noise transfer
curve is plotted in Fig. 2. The result shows that the center fre-
269 kHz and near to the loop bandwidth of the PLL
is 280 MHz/V before compensation and the
is 15 MHz/V after compensation. Based on the de-
Fig. 2. Simulated supply noise transfer curve.
Fig. 3. (a) Ring VCO delay cell and (b) its supply voltage sensitivities.
3.71 Mrad/s591 kHz . The maximal gain at this
center frequency is 53.5 dB before calibration and 28.1 dB after
calibration, respectively. Besides, the supply voltage sensitivity
of the PLL is defined as
PLL is also suppressed. On the other hand, the 3-dB bandwidth
3.71 Mrad/s 591 kHz of this second-
order band-pass characteristic would determine the frequency
range disturbed by the supply noise.
is reduced, the supply voltage sensitivity of the
594IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 19, NO. 4, APRIL 2011
Fig. 4. VCO with 5-bit digital-controlled opposite-supply-sensitivity pair and the switch-controlled supply voltage.
B. Supply Voltage Sensitivity Suppression
In order to reduce the supply voltage sensitivity and the gain
, a ring VCO is realized by the delay cells with an op-
posite-supply-sensitivity pair in Fig. 3(a). The pMOS transis-
tors M1 and M2 are used to be the input differential pair due to
less sensitive to supply voltage variation compared with nMOS
type. In addition, the cross-coupled pair, diode-connected load,
and voltage-controlled current load are all located in the bottom
part so as to avoid the supply noise disturbance in the top part
of the ring VCO cell. When the source voltage Va of the input
differential pair is increased, the transconductance and current
driving capacity are also enhanced to result in increasing the os-
cillation frequency of a VCO. So this VCO has a positive sensi-
tivity related to this voltage Va. The sensitivity curve is shown
on the curve (A) in Fig. 3(b) and the slope is given as
The opposite-supply-sensitivity pair is composed of the
pMOS transistors M3 and M4 which has the negative sensi-
tivity related to the voltage Vb. When the input differential
pair is turned on, the additional opposite-supply-sensitivity pair
which is viewed as the constant current source slightly shortens
the rising time. On the other hand, when the input differential
pair is turned off, the additional opposite-supply-sensitivity
pair still charges the output and it heavily extends the falling
time. The net impact on the frequency is the combination of
the rising and falling times. As a result, the extending falling
time dominates over the shortening rising time and the re-
sulting frequency is reduced. When the source voltage Vb of
the opposite-supply-sensitivity pair is increased, the transcon-
ductance and current driving capacity are also enhanced to
result in decreasing the oscillation frequency of a VCO. So
this VCO has a negative sensitivity related to this voltage Vb.
The sensitivity curve is shown on the curve (B) in Fig. 3(b)
and the slope which is proportional to the aspect ratio of the
opposite-supply-sensitivity pair is given as
factor is determined by the aspect ratio of the opposite-
Finally, the voltages Va and Vb are connected together to
cancel the positive sensitivity of the conventional differential
pair with the negative sensitivity of the opposite-supply-sensi-
tivity pair in a ring VCO. The sensitivity curve is shown on the
curve (C) in Fig. 3(b) and the resulting slope is given as
Based on the ring VCO delay cell in Fig. 3(a), the proposed
three-stage ring VCO with a 5-bit digital-controlled opposite-
supply-sensitivity pair and the switch-controlled supply volt-
ages  is realized in Fig. 4. The internal supply voltage for
this VCO is controlled by the switches, S0, S1, and S2, re-
pect ratios of the opposite-supply-sensitivity pair are binary-
weighted and the digital-controlled pair is turned off initially.
In this topology, because of the directly embedded compensa-
tion pair in the ring VCO which results in shorter compensation
path, the phase delay and amplitude attenuation of compensa-
tion in frequency response is alleviated. Owing to the process
variations, a digital calibration circuit is employed to select the
aspect ratio of the opposite-supply-sensitivity pair and equiva-
lently decide the factor of
. Besides, the as-
if critical compensated
While the aspect ratio of the opposite-supply-sensitivity pair
is determined by using the digital calibration circuit, then the
and the overall supply voltage sensitivity are sig-
C. Digital Calibration Technique
The flowchart for the digital calibration technique is shown
in Fig. 5. The supply voltage sensitivity of the VCO is detected
based on the frequency comparison. Initially, switch S0 on the
allthecontrol bitsoftheSARcontroller are reset.Then thePLL
KAO AND LIU: DIGITALLY-CALIBRATED PLL WITH SUPPLY SENSITIVITY SUPPRESSION595
Fig. 5. Flowchart for the digital calibration technique.
to S2 for detecting the supply voltage sensitivity. Also, the SAR
ibration process repeats five rounds for a 5-bit adaptive oppo-
site-supply-sensitivity pair embedded in the ring VCO. Finally,
all of the control bits are determined and maintained so that
the supply voltage sensitivity is near to zero. Now, the supply
voltage of the VCO is switched to S1 and in phase-locking op-
eration. Compared with the timing jitter before calibration, it
could be reduced after calibration when the noise is applied to
the supply voltage of the VCO.
III. CIRCUIT DESCRIPTION
A. Proposed PLL
This PLLis composed ofa ring VCO embeddedwith thedig-
divider with a division ratio from 45 to 54, a second-order loop
filter, and a digital calibration circuit as shown in Fig. 6. The ad-
ditional digital calibration circuits include a frequency detector
(FD), a 5-bit SAR controller, and a divider chain whose division
ratio is equal to 512. The parameters for this PLL are listed in
Table I. The loop bandwidth of 565 kHz and phase margin of
66 are designed for this PLL.
Initially, this PLL is locked at 1.5 GHz when the switch S0
is turned on. Then the switch Tg is turned off to disconnect the
charge pump with the passive loop filter. At this time, the oscil-
lation frequency of the VCO is changed by switching S0 to S2
to vary the supply voltage. The frequency deviation is detected
by the frequency detector (FD) and the 5-bit SAR controller to
update the aspect ratio of the opposite-supply-sensitivity pair
to reduce the supply voltage sensitivity. When the LSB is deter-
mined, thefrequencydeviationcouldbe limited inthe
offset range for the VCO of 1.5 GHz. After the digital calibra-
tion completed, the switches S1 and Tg are turned on and the
corresponding internal supply is adopted. This PLL will lock
again and its overall supply voltage sensitivity is expected to be
low after the calibration. Moreover, since the digital calibration
circuits are disabled once the calibration is completed, the addi-
tional power consumption and digital switching noise from the
calibration circuits are turned off. The key building blocks and
simulation results will be illustrated in the following.
596IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 19, NO. 4, APRIL 2011
Fig. 6. Digitally-calibrated PLL with supply sensitivity suppression.
B. Frequency Detector
In the calibration loop, the input clock period of the 5-bit
SAR controller is a critical parameter to affect the precision of
calibration result. If the input clock period is too long, the total
period is shorter than the FD’s response time, the calibration
result may be incorrect. So the FD’s response time is inspected
in Fig.7(a). Thefeedback clock
In Fig. 7(b), assume that the quadrature clocks
are faster than the clock . The sampling edges of the clock
will run rightward due to the frequency deviation. Hence
the FD’s longest response time in terms of the number of the
input reference clock,
and input reference clock
tion between the feedback clock and the input reference clock.
For precision consideration, the FD is desired to detect a 5 MHz
frequency deviation for the VCO of 1.5 GHz. Therefore,
is calculated at 300. To tolerate the nonlinearity of the FD, the
5-bit SAR controller’s clock is realized by dividing the clock
is equal to 30 MHz andis the frequency devia-
C. 5-Bit SAR Controller
in Fig. 8. The operation principle is described in the following.
the digital calibration is enabled, it is set to high to start the bi-
nary search action. When the first clock arrives, the most sig-
nificant bit (MSB)
is set to high. The MSB will then be
maintained or changed to low based on the comparison result
from theFD output at thenextclock edge and the nextbit
is set to high. Finally, the process will repeat five rounds until
the least significant bit (LSB)
SAR controller also generates a signal, “Stop,” to indicate the
completion of the digital calibration procedure.
is determined. The 5-bit
Fig. 7. (a) FD and (b) response time.
D. Simulation Results
The simulated supply voltage sensitivity of the ring VCO
operating at 1.5 GHz is shown in Fig. 9. When the opposite-
supply-sensitivity pair code
voltage sensitivity is positive and
plotted in curve (1). If the opposite-supply-sensitivity pair code
is equal to 16, the supply voltage sensitivity is near
to zero and
15 MHz/V as plotted in curve (2). Fi-
nally, the opposite-supply-sensitivity pair code
set to 31, then the supply voltage sensitivity is negative and
320 MHz/V as plotted in curve (3). The simulated
supply voltage sensitivity versus code
Fig. 10. It indicates that the supply voltage sensitivity of the
VCO is varied from positive initially to negative if the dig-
increase the aspect ratio of the opposite-supply-sensitivity pair.
And the average supply voltage sensitivity step is
is equal to 0, the supply
280 MHz/V as
is shown in
is increased; it is equivalent to
KAO AND LIU: DIGITALLY-CALIBRATED PLL WITH SUPPLY SENSITIVITY SUPPRESSION597
Fig. 8. Five-bit SAR controller.
Fig. 9. Simulated supply voltage sensitivity at: (1) undercompensated; (2) crit-
ical compensated; (3) overcompensated.
Fig. 10. Simulated supply voltage sensitivity versus digital-controlled code
????? ? ??.
simulated peak-to-peak jitter of the VCO output would be min-
imized if the supply voltage sensitivity is equal to zero. Other-
Fig. 11. Die photograph.
wise, it could be increased even if the sensitivity is positive or
IV. EXPERIMENTAL RESULTS
This chip has been fabricated in a 0.18- m CMOS 1P6M
technology as shown in Fig. 11. The total chip area and core
area occupy 1.423 and 0.235 mm , respectively. The measured
tuning curve of the VCO with supply voltage switch S0 turned
on and all bits reset is plotted in Fig. 12. This measured tuning
curve of the VCO covers a frequency range from 0.95 to 2 GHz
and the measured locking range of this PLL is from 1.25 to
1.75 GHz. When the operating frequency is at 1.5 GHz with
clean power supply, the measured reference spur level is -53
dBc as shown in Fig. 13. Fig. 14 shows the measured phase
noise at 1-MHz offset frequency is -96 dBc/Hz. Meanwhile,
from the measured jitter histogram, the rms jitter and peak-to-
598IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 19, NO. 4, APRIL 2011
Fig. 12. Measured tuning curve of the VCO.
Fig. 13. Measured reference spur level at 1.5 GHz.
Fig. 14. Measured phase noise at 1.5 GHz.
peak jitter are 1.9 and 15.1 ps, respectively. The measured fre-
quency switching transient response in Fig. 15 shows that the
up switching time is 18 s and the down switching time is 26 us
Fig. 15. Measured frequency switching transient response from 1.475 to 1.525
GHz and vice versa.
Fig. 16. Measurement setup.
when the synthesizer is switched from 1.475 to 1.525 GHz and
vice versa. The total power consumption at 1.8 V is 16.2 mW
for the operating frequency of 1.5 GHz.
To verify the supply noise suppression and sensitivity re-
duction technique mentioned above, the measurement setup is
shown in Fig. 16. A sinusoidal waveform with the amplitude of
100 mVpp acts as the supply noise source and it is ac-coupled
to the clean power supply which is connected to the VCOVDD
pad. The noise frequency is altered from 1 kHz to 100 MHz
in order to observe the effect of output spectrum and jitter his-
togram when operating frequency at 1.5 GHz.
Before calibration, the measured supply noise spur level with
noise frequency at 10 kHz is shown in Fig. 17(a). The result
indicates that low frequency supply noise almost does not af-
fect the output spectrum and jitter histogram performance. With
noise frequency at 110 kHz as shown in Fig. 17(b), the mea-
sured output spectrum would be spread. Meanwhile, the mea-
sured rms and peak-to-peak jitter are degraded to 16.5 and 59.1
ps, respectively. When the applied supply noise frequency is at
1, 10, and 100 MHz, the supply noise spurs appear in the output
spectrum as shown in Fig. 17(c)–(e), respectively. Because of
the band-pass characteristic for the supply noise of the PLL, the
jitter histogram performance would be degraded slightly even
KAO AND LIU: DIGITALLY-CALIBRATED PLL WITH SUPPLY SENSITIVITY SUPPRESSION599
Fig. 17. Measured supply noise spur level with noise frequency at: (a) 10 kHz;
(b) 110 kHz; (c) 1 MHz; (d) 10 MHz; and (e) 100 MHz.
if the supply noise spurs exist. The ac-coupled noise source to
power supply can be seen as amplitude modulation noise
of the VCO as
VCO, noise frequency, and modulation factor, respectively,
which is proportional to the amplitude of the noise source. So
the output is rewritten as
,, and denote the operating frequency of the
Equation (15) indicates that the supply noise spurs would
emerge on the output spectrum with the amplitude modulation
noise on the supply voltage.
The measured output spectrum and jitter performance are af-
fected most severely for the supply noise frequency of 110 kHz.
Compared with the nature frequency of 269 kHz mentioned in
Section II-A, the deviation is caused due to the additional ca-
pacitor C2 in loop filter. The measured spectra without and with
digital calibration are shown in Fig. 18(a) and (b), respectively.
After calibration, the spread spectrum caused by supply noise
can be shrunk and the measured reference spur is reduced from
56.8 to62.8 dBc. Meanwhile, the measured jitters without
and with digital calibration are shown in Fig. 19(a) and (b), re-
spectively. The rms jitter is reduced from 16.5 to 9.7 ps and the
peak-to-peak jitter is reduced from 59.1 to 48.4 ps. So this PLL
achieves the rms jitter improvement by a factor of 41.2%. The
shrunk spectrum and reduced jitter after calibration are mea-
sured to verify the suppression of supply voltage sensitivity.
The measured jitter versus supply noise frequency is plotted
in Fig. 20 without and with digital calibration. The measure-
ment results confirm the band-pass filter characteristic for the
supply noise model of the PLL mentioned in Section II. The
measured jitter would be reduced after calibration near to the
nature frequency. On the other hand, the measured jitter would
due to the addition with thermal and flicker noise of transistors
M3 and M4 embedded in the proposed ring VCO as shown in
Fig. 4. Simulation result also indicates that the phase noise is
worsened by 2.5 dB at 1-MHz offset.
Considering the line transient response, a square waveform
power supply. The measured performance is degraded more
than that with sinusoidal waveform for the frequency of 110
kHz. The measured jitters without and with digital calibration
are shown in Fig. 21(a) and (b), respectively. The rms jitter is
reduced from 21.1 to 12.2 ps and the peak-to-peak jitter is re-
duced from 76.4 to 50.7 ps. Meanwhile, the measured spectra
without and with digital calibration are shown in Fig. 22(a)
from 1.49813 to 1.50165 GHz. With calibration, the frequency
modulation waveforms without and with digital calibration are
600IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 19, NO. 4, APRIL 2011
Fig. 18. Measured spectra (a) without and (b) with calibration for the supply noise frequency of 110 kHz.
Fig. 19. Measured jitters (a) without and (b) with calibration for the supply noise frequency of 110 kHz.
Fig. 20. Measured jitter without and with calibration circuits versus supply
also shown in Fig. 23(a) and (b), respectively. The range of fre-
quency modulation caused by supply noise is shrunk from 3.75
to 1.36 MHz. Fig. 24 shows the measured jitter versus oper-
ating frequency of this PLL. It indicates that the supply sen-
sitivity suppression is achievable over the operating frequency
range from 1.35 to 1.62 GHz.
Finally, Table II gives the performance summary of the pro-
posed PLL and comparison with other literatures. The area of
digital calibration circuits and programmable divider occupies
two thirds of the total core area and can be further reduced with
supply voltage sensitivity. The power consumption is reduced
otherworks, thebetterresolution ofaveragesupplyvoltagesen-
sitivity step which is
A digital calibration technique to suppress the supply voltage
sensitivity of a PLL is presented. The band-pass characteristic
KAO AND LIU: DIGITALLY-CALIBRATED PLL WITH SUPPLY SENSITIVITY SUPPRESSION 601
Fig. 21. Measured jitters (a) without and (b) with calibration for the square wave supply noise at frequency of 110 kHz.
Fig. 22. Measured spectra (a) without and (b) with calibration for the square wave supply noise at frequency of 110 kHz.
Fig. 23. Measured frequency modulation waveforms (a) without and (b) with calibration for the square wave supply noise at frequency of 110 kHz.
for the supply noise model of the PLL is also analyzed and ver-
ified with measurement results. In order to reduce supply-in-
duced jitter, the voltage-controlled ring oscillator is designed
to embed an opposite-supply-sensitivity pair to suppress supply
noise. Besides, the added compensation pair which has adap-
tive negative supply voltage sensitivity in the ring VCO could
Because the calibration loop is turned off once the calibration is
completed, this method consumes much less power compared
tionally. With the applied 100 mVpp 110 kHz sinusoidal wave-
form noise ac-coupled to the supply, the rms jitter is reduced
602 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 19, NO. 4, APRIL 2011
Fig. 24. Measured jitter versus operating frequency.
SUMMARY AND COMPARISON
from 16.5 to 9.7 ps after calibration while operating at 1.5 GHz.
So this PLL achieves the rms jitter improvement by a factor of
41.2% under digital calibration mechanism.
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Shih-Yuan Kao was born in Tainan, Taiwan, in
1984. He received the B.S. degree in electrical
engineering from National Cheng Kung University,
Tainan, Taiwan, in 2006. He is currently pursuing
the Ph.D. degree in electronics engineering from
National Taiwan University, Taipei, Taiwan.
His research interests include phase-locked loops
and high-speed CMOS data-communication circuits
for multiple gigabit applications.
in Keelung, Taiwan, in 1965. He received the B.S.
and Ph.D. degrees in electrical engineering from Na-
tional Taiwan University (NTU), Taipei, Taiwan, in
1987 and 1991, respectively.
During 1991–1993, he served as a second lieu-
tenant in the Chinese Air Force. During 1991–1994,
he was an Associate Professor with the Department
of Electronic Engineering, National Taiwan Insti-
tute of Technology. He joined the Department of
Electrical Engineering, NTU, in 1994, where he has
been a Professor since 1998. His research interests include analog and digital
integrated circuits and systems.
Dr. Liu has served as chair of the IEEE SSCS Taipei Chapter in 2004–2008,
which achieved the Best Chapter Award in 2009. He has served as general
chair of the 15th VLSI Design/CAD Symposium, Taiwan (2004) and as
Program Co-chair of the Fourth IEEE Asia-Pacific Conference on Advanced
System Integrated Circuits, Fukuoka, Japan (2004). He was the recipient of the
Engineering Paper Award from the Chinese Institute of Engineers in 2003, the
Young Professor Teaching Award from MXIC Inc., the Research Achievement
Award from NTU, and the Outstanding Research Award from National Science
Council in 2004. He has served as a technical program committee member for
ISSCC in 2006–2008 and A-SSCC since 2005. He was an Associate Editor
for IEEE JOURNAL OF SOLID-STATE CIRCUITS in 2006–2009 and a Guest
Editor for IEEE JOURNAL OF SOLID-STATE CIRCUITS Special Issue in 2008
December. He was an Associate Editor for IEEE TRANSACTIONS ON CIRCUITS
AND SYSTEMS—II: EXPRESS BRIEFS in 2006–2007. He was an Associate Editor
for IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS
in 2008–2009. He was the Editorial Board of Research Letters in Electronics
in 2008–2009. He is also an Associate Editor for IEICE (The Institute of
Electronics, Information and Communication Engineers) Transactions on
Electronics from 2008. He is an Associate Editor for ETRI Journal, and also an
Associate Editor for Journal of Semiconductor Technology and Science, Korea,
from 2009. He is a member of IEICE.