Effective operating system scheduling domain hierarchy for core-cache awareness
ABSTRACT With the introduction of multi-core processors, a balance between access contention of the cache and availability of cached data for multiple cores has to be addressed. Processor manufacturers are finding this compromise through a combination of private and shared cache structures, where the last level cache (LLC) may not be shared across all processing cores. This poses an interesting opportunity for the operating system in ensuring minimum access time to the memory for optimal performance. Our proposed solution is to augment an existing scheduling domain hierarchy to be aware of the relationship between the processing cores and their respective LLCs in order to achieve improved performance. We focus on LLCs as the access time between local caches is minimal as compared to remote caches or main memory. In this paper, we show that there are marked improvements using a LU scientific benchmark and a chat-server application benchmark.