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582IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 33, NO. 3, AUGUST 2010

A Power Bus With Multiple Via Ground Surface

Perturbation Lattices for Broadband Noise Isolation:

Modeling and Application in RF-SiP

Chia-Yuan Hsieh, Chuen-De Wang, Kun-You Lin, Member, IEEE, and Tzong-Lin Wu, Senior Member, IEEE

Abstract—A model and application of the power bus with

multiple via ground surface perturbation lattice (MV-GSPL) is

investigated in this paper. A 1-D model especially considering

the multiple via effects of the MV-GSPL inside the long period

coplanar electromagnetic bandgap power planes (LPC-EBG) is

proposed. This model can explain the mechanism of the stopband

enhancement and accurately predict the effect of multiple via on

the stopband behavior. The accuracy of this model is verified both

by full-wave simulation and experiments. Based on this model, a

MV-GSPL power/ground pair is designed on a radio-frequency

(RF) package for system-in-package (SiP) application. A test

C-band LNA fabricated by the TSMC 0.18- m 1P6M process is

packaged on the MV-GSPL substrate for noise immunity test.

Both the chip-package co-simulation and experimental results

show excellent power noise isolation capability of the RF-SiP

package.

Index Terms—Electromagnetic bandgap (EBG), ground bounce

noise (GBN), high-speed digital circuits, mixed-signal system, si-

multaneous switching noise (SSN).

I. INTRODUCTION

W

package (SoP), designers are required to implement a compli-

cated system in a compact substrate [1], [2]. With the clock

rate of digital systems is increasing, simultaneous switching

noise (SSN) or so-called power/ground bounce noise (GBN)

becomes one of the most critical issues. When high-speed dig-

ital circuits are switching or signal vias transit between power/

ground planes, shunt through currents may excite the resonance

modes of power distribution networks (PDNs). The resonating

PDN may excite undesired electromagnetic energy propagating

within it [3], or even cause electromagnetic interference prob-

lems [4]. Moreover, this issue becomes worse in mixed signal

SiP systems since these noise sources might be implemented

ITH the trend of high integration schemes of electronic

systems such as system-in-package (SiP) or system-on-

Manuscript received August 10, 2009; revised October 18, 2009; accepted

November03,2009.FirstpublishedJanuary19,2010;currentversionpublished

August 04, 2010. This work was supported by the National Science Council,

Taiwan under Grant NSC 95-2221-E-002-182 and 98R0062-3, and partially

supported by Excellent Research Projects of National Taiwan University under

Grant 98R0062-3. This work was recommended for publication by Associate

Editor M. Cases upon evaluation of the reviewers comments.

The authors are with the Department of Electrical of Engineering and Grad-

uate Institute of Communication Engineering, National Taiwan University,

Taipei 10617, Taiwan (e-mail: wtl@cc.ee.ntu.edu.tw).

Color versions of one or more of the figures in this paper are available online

at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TADVP.2009.2036858

much closer to radio-frequency (RF) sensitive circuits or analog

circuits. SSN can easily couple to these sensitive circuits and

may degrade their performance.

In recent years, many researchers have contributed to apply

electromagnetic bandgap structure (EBG) to suppress the SSN

coupling. The mushroom-type and coplanar-type electromag-

netic bandgap structures are two main types of topologies

[5]–[7]. The former type deals with three-layer stack forming

a high impedance surface structure between power/ground

planes, while the latter is concerned with two-layer stack with

a periodically etched power or ground plane. Both types of

structures combine EBG periodic structure with the designs of

power/ground planes.

SinceSSNnoiseinpackagesisbroadband,severalresearches

have conducted to increase the noise stopband of EBG struc-

ture. Mushroom type EBG with high dielectric constant thin

film [8], the artificial-substrate EBG (AS-EBG) [9], or hybrid-

planar-type EBG structure [10] have been proposed using some

extra elements such as high-DK rods or SMT elements. Despite

these works having demonstrated enhanced performance, using

extra elements may increase the cost at the same time. Further-

more, the stopband can be improved directly by changing geo-

metric design such as using spiral via for mushroom type EBG

or meandering bridge pattern between patches of coplanar EBG

[11], [12]. These approaches, however, may increase the stop-

band but complicate the design layout.

Recently, another bandwidth enhancement technique has

been demonstrated by embedding the multiple via ground

surface perturbation lattice (MV-GSPL) in parallel-plate

power/ground pair or the coplanar EBG structure [13], [14]. It

is a three layer periodic structure. The top layer is a coplanar

EBGpatternandbottomlayerisagroundplane.TheMV-GSPL

is a square metal patch on middle layer with multiple vias elec-

trically connecting to the ground plane. The lattices can be

distributed within the power/ground plane pair periodically.

The stopband can be significantly increased without any arti-

ficial materials required, but the mechanism of the bandwidth

enhancement and the corresponding design models have not

been proposed.

In this work, a 1-D model especially considering the mul-

tiple via effects of the ground surface perturbation lattice in-

side the long period coplanar electromagnetic bandgap power

planes (LPC-EBG) [6] is proposed. This model can explain the

mechanism of the stopband enhancement and accurately pre-

dict the effect of multiple vias on the stopband behavior. Based

on this model, a MV-GSPL power/ground pair is designed on

1521-3323/$26.00 © 2010 IEEE

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HSIEH et al.: A POWER BUS WITH MULTIPLE VIA GROUND SURFACE PERTURBATION LATTICES FOR BROADBAND NOISE ISOLATION583

Fig. 1. The embodiment view of a 3?3 unit-cells LPC-EBG power/ground

pair with LPC-EBG.

a RF package substrate for SiP application. A test C-band low

noise amplifier (LNA) fabricated by the TSMC 0.18 m 1P6M

processispackagedontheMV-GSPLsubstratefornoiseimmu-

nitytest.Boththechip-packageco-simulationandexperimental

results show excellent power noise isolation capability of the

RF package for the C-band LNA. The proposed EBG structure

is confirmed possessing up to 50% spurious noise reduction in

output spectrum of the LNA.

This paper is organized as follows. In Section II, the

topology and design concept of the MV-GSPL embedded

inside of LPC-EBG structures is presented followed by the

descriptions of the 1-D analysis model and its stopband pre-

diction method. In Section III, the accuracy of the proposed

model is verified by comparing with full-wave simulations

and measured S-parameter responses. Through the proposed

model, a series of design curves are constructed to discuss the

quantitative relationship between the MV-GSPL geometric

parameters and the stopband. In Section IV, the case study of

the noise isolation on a C-band LNA package with embedded

MV-GSPL is presented. Conclusions are drawn in Section V.

II. MODELING OF MULTIPLE VIA GROUND SURFACE

PERTURBATION LATTICE

A. Design Concept of LPC-EBG Power Layer With MV-GSPL

Fig. 1 shows the embodiment view of a 3

LPC-EBG power/ground pair with MV-GSPL. It is a three

layer periodic structure. The top layer is a LPC-EBG pattern. It

consists of a square pad with bridges on the four sides. The ad-

jacent cellsare connectedthrough thebridges.Thebottom layer

is a solid ground plane. The MV-GSPL is a square metal patch

on middle layer with multiple vias electrically connecting to

the ground plane. The geometrical parameters of this structure

are shown in Fig. 2. As shown in Fig. 2(a), the corresponding

geometrical parameters of the etched EBG power plane are de-

noted as

. Fig. 2(b) shows the layer stackup

parameters, including the side length of unit-cell , the width

of square patch

, and two layer thicknesses

It has been know that the lower-edged stopband

conventional LPC-EBG is determined by the series inductance

of the bridge and shunt capacitance of the etched EBG pattern

[6]. On the other hand, the upper-edged stopband

LPC-EBG is limited by the cavity resonance of unit-cell [10].

Therefore, the unit-cell size determines the

3 unit-cells

and.

of the

of

. The enhanced

Fig. 2. Overall geometric parameters: (a) etched power plane; (b) stackup pa-

rameters.

Fig. 3. Electric field distribution of second-order mode. (a) LPC-EBG. (b)

LPC-EBG with MV-GSPL.

stopband of the LPC-EBG with MV-GSPL embedded is

achieved by simultaneously decreasing

The MV-GSPL increases the shunt capacitance of LPC-EBG

and thus achieves lower

.

Also, the

of LPC-EBG is increased due to the MV-GSPL

onthecavityresonance. The MV-GSPL maydominatetheunit-

cell cavity resonance, making

of the etched pattern. This idea can be demonstrated by exam-

ining the electric field distribution for a unit-cell.

Fig. 3(a) and (b) shows the patterns of electric field distribu-

tionofsecond-order modeofLPC-EBGonlyandtheLPC-EBG

with MV-GSPL obtained by numerical tool HFSS. We consider

the lossless dielectric and ideal conductor for our simulations. It

can be shown that the peak strength is around the etched pattern

due to the self-resonance of unit-cell but near the center of the

unit-cell for LPC-EBG with MV-GSPL. Therefore, the cavity

dimension formed by square patch of MV-GSPL at the second

layer and the LPC-EBG on top layer may control the resonance

frequency (or

) of the unit-cell.

Becausethe viasconnecting thepad and thegroundplane is a

part of the lattice, the numbers and locations of the vias will sig-

nificantly influence the cavity resonance behavior. If the cavity

resonanceisconsideredasseriesresonanceofshuntcapacitance

of MV-GSPL and the total via inductance, the

as the total via inductace is decreasing. Intuitively, this can be

ahievedby increasing thenumbersof vias. Therefore,fivekinds

of via patterns as shown in Fig. 4 will be discussed. The vias’

locations are kept in reflection symmetry to the horizontal and

vertical axis and along the edges of the pad. Fig. 4(a) and (b)

shows the four-via cases. Fig. 4(c) and (d) shows the five-via

cases, and Fig. 4(e) shows the eight-via case. The cases of more

and increasing.

not constraint only by the size

is able to rise

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584 IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 33, NO. 3, AUGUST 2010

Fig. 4. The five proposed via-posted pattern: (a) 4-via-1, (b) 4-via-2, (c)

5-via-1, (d) 5-via-2, (e) 8-via.

than eight vias are not considered because of the difficulty in

implementation. The radius of the via is denoted as

in Fig. 4(e).

as shown

B. One-Dimensional Equivalent Circuits Model Considering

Via Effect

In order to predict the stopband of the MV-GSPL structure

with the impact of via pattern, a 1-D equivalent circuit model is

developed, as shown in Fig. 5. The unit-cell is decomposed into

two types of sections denoted by Aand B, as shown in Fig. 5(a).

The corresponding equivalent circuit for each section is shown

in Fig. 5(b). Section A consists of the conductor-back coplanar

waveguide (CB-CPW) and a short parallel plate structure.

modelstheinductanceoftheCB-CPWwithasmallmicro-stripe

line between unit-cells, and

allel plate structure.

models the total capacitance in section

A which is mainly contributed from the parallel plate structure.

The values of these three circuits are calculated using the fol-

lowing equations:

models the inductance of par-

(1)

(2)

(3)

where

space,

micro-stripe and CB-CPW structure,

free space, and

tric constant of substrate, the effective dielectric constants of

micro-stripe and CB-CPW.

Section B accounts for the three-layer MV-GSPL structure

at the center of the unit-cell. As noted by three auxiliary lines

on emphasizing view of section B in Fig. 5(a),

section B is further segmented so as to consider the via effect

through calculating the total inductance value to ground on

these three auxiliary lines. As shown in Fig. 5(b),

model the parallel plate inductance between the power layer

and the patch layer with mutual inductive coupling

is related the magnetic flux for the current loop from patch

to the ground. The mutual inductance between power and

patch is related to the current loop of the overlapping area,

and are the permittivity and permeability of free

are the characteristic impedance of

is the light speed of

are the relative dielec- and

and

.

Fig. 5. Proposed one-dimensional equivalent circuit: (a) Unit-cell corre-

sponding partitions, (b) proposed circuit.

which is equal to the current loop between patch layer and the

bottom (ground) layer [15].

between the power and the patch layer and

the capacitance between the patch and the ground layer. For

maintaining symmetry,

and

and , respectively. All circuit values are calculated using

equations

and model the capacitance

and model

are set equal to

(4)

(5)

(6)

(7)

and model the total inductance shorting to the ground

and (or), respectively. Their values vary as

the vias’ arrangement along the direction of each auxiliary line

change. Accurate estimation of

the accuracy of the stopband prediction. Fig. 6(a)– (c) shows

three possible via arrangements along

three arrangements can compose all possible via patterns in

Fig. 4(a)–(e). An intuitive way to calculate

considering the shunting effect of the vias inductance

They are

, and

viacasesshowninFig.6(a),(b),and(c),respectively.Thisintu-

itive estimation will be good enough in the proposed 1-D model

along

and is important for

( or ). These

(or) is just

.

for the one, two, and three

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HSIEH et al.: A POWER BUS WITH MULTIPLE VIA GROUND SURFACE PERTURBATION LATTICES FOR BROADBAND NOISE ISOLATION585

Fig. 6. Three possible via arrangements along ? , (?

posted, (b) one via-posted, (c) two via-posted.

or ? ): (a) one-via

Fig. 7. The ideal 2-D current paths from patch to the ground plane through the

via of one via posted case.

to the

direction of the auxiliary lines should be accounted as the 2-D

effect in higher frequency becomes obvious. It will be shown in

next section that the accuracy of the 1-D model can be signifi-

cantly improved in predicting the upper edge cutoff frequency

afterconsidering theexcessinductanceintheestimationof

(or ). Following will discuss the method of calculating

the excess inductance.

Basically, a 1-D model only considers the current distribu-

tion in one direction and the inductive effect of the orthogonal

directionofcurrentisnotincluded.Becausethe2-Dcurrentdis-

tribution is complicated, the average concept is used to estimate

the excess inductance. Taking the one via case along

example, Fig. 7 shows ideally 2–D current paths from patch to

the ground plane through the via. As can be seen in Fig. 7, each

currentpathonthepatchisassumedflowingintheauxiliaryline

direction to count the associated excess inductance. For one via

caseinFig.6(a),theexcessinductance

the direction of the auxiliary lines for the th (or (

current path is

. However, the excess inductance of the patch along the

as an

contributedfrom

th)

(8)

where

possible current paths. The total inductance (

cluding the via and the excess inductance can be estimated by

the average as

, and is the total

or ) in-

(9)

Similarideacanbeappliedtothecaseoftwoviasasshownin

Fig. 6(b), but there are two possible excess inductances (

and ) for each ideal current path . They are

(10)

(11)

The total inductance (

cess inductances and the corresponding via inductance can also

be obtained by average as

or) by shunting these two ex-

(12)

Similarly,thetotalinductance(

can be derived as

or )forthreeviascase

(13)

The analytic form cannot be obtained due to the complicated

shunting equations, but theycan be calculated easily by the help

of computer.

C. Stopband Prediction

The lower-edged stopband

can be estimated efficiently based on this model. For

mainly determined by series inductance between unit-cells and

the capacitance to the ground (or MV-GSPL) of the unit-cell

because of the low frequency approximation. Consequently, the

circuit in Fig. 5(b) can be simplified by considering only the

dominant effect. The simplified circuit, shown in Fig. 8 which

consists of circuit element

and

and the upper-edged stopband

, it is

defined as follows:

(14)

(15)

where

riodic boundary condition on the simplified circuit and setting

the phase shift equal to 180 ,

is the total number of the vias. Through applying pe-

is derived as

(16)

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586 IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 33, NO. 3, AUGUST 2010

Fig. 8. The simplified circuit for ? prediction.

TABLE I

DESIGN SAMPLE PPARAMETER SUMMARY

From (16), it reveals that

through increasing the capacitance between the top layer and

the plate or the inductance of the via. On the other hand, since

is determined by the cavity resonance of the unit-cell, it can

be predicted by calculating the first resonance frequency of the

unit-cell using the complete equivalent circuit in Fig. 5(b).

is possible to be decreased

III. DESIGN PARAMETERS ANALYSIS USING PROPOSED MODEL

A. Accuracy Check for Proposed Model

The accuracy of the proposed model is verified using

full-wave simulation (HFSS). The

of via patterns in Fig. 4 are calculated both by the equivalent

model and the full-wave simulation. The dimensions of the

unit-cell and their corresponding

Table I. The

and in Table I are calculated by (9), (12),

or (13). The bangap predicted by the intuitive estimation of

, or

three via-posted cases on each auxiliary line are also shown for

comparison.

Fig. 9 shows the comparison of bandgap prediction between

full-wave simulation and the proposed model. As can be seen

in Fig. 9, the bandgap (between

be fairly predicted using the proposed model. It is also seen that

the intuitive model of the multiple via inductance is not accu-

rate enough (over estimation) for predicting the

andof those five types

andvalues are listed in

for the one via, two vias, and

and) of the five cases can

. In addition

Fig. 9. The bandgap predition between models and HFSS.

Fig. 10. Eight-via sample photo with measured ports locations marked.

to the accuracy information, Fig. 9 also indicates that the pro-

posed model is capable of predicting the ascent of

number of via is increased. There is little deviation between dif-

ferent via patterns that have the same numbers of via. In all the

via patterns, the eight-via case possesses the highest

forming the design concept mentioned in Section II. As a result,

increasingthenumberofviaandremainingotherdesignparam-

eters unchanged tend to enhance the stopband for the proposed

EBG structure.

The accuracy of the proposed circuit model is further exper-

imentally verified. Three test boards are fabricated in the FR4

substrate. They are the cases of 4-via-2, 5-via-2, and 8-via. The

geometric parameters of the unit-cell are the same as shown in

Table I. The board size is 60 mm

Through-hole vias are implemented with anti-via radius

mm. Two ports insertion loss measurements are conducted and

compared with model-predicted results to validate the accuracy

of the model. Fig. 10 shows the photo of the fabricated board

of the 8-via case and the port locations. All three cases are

measured at the same locations using SMA connectors. Fig. 11

shows the measurement results marked with model-predicted

stopband bandwidth of three EBG boards. According to the

measurement results from dc to 5 GHz, the stopband of three

cases could be well predicted using the proposed model. Again,

as the

, con-

60 mm with 33 unit-cells.