Advanced high-κ dielectric stacks with polySi and metal gates: Recent progress and current challenges
ABSTRACT The paper reviews our recent progress and current challenges in implementing advanced gate stacks composed of high-κ dielectric materials and metal gates in mainstream Si CMOS technology. In particular, we address stacks of doped polySi gate electrodes on ultrathin layers of high-κ dielectrics, dual-workfunction metal-gate technology, and fully silicided gates. Materials and device characterization, processing, and integration issues are discussed.
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ABSTRACT: Ballistic performance of nanoscale In 0.3 Ga 0.7 Sb double gate n-MOSFET is studied for different gate oxides considering same Equivalent oxide thickness (EOT). Non equilibrium greens function method is utilized under the environment of well-known SILVACO's ATLAS device simulation package to carry out the simulation. Wave function penetration to the oxide is taken into account in the simulation. The results obtained from the simulation indicate that EOT is not solely control the device performance. Rather, a strong correlation is found between the I-V characteristics and the conduction band offset (E C) of the channel and dielectric materials. It is also found that the threshold voltage decreases and the subthreshold swing increases with the higher value of E C . It reveals that for nanoscale MOSFET design, another tunable variable is found to ensure best performance.8th International Conference on Electrical and Computer Engineering (ICECE 2014), Dhaka, Bangladesh; 12/2014
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ABSTRACT: Different high-k dielectrics have been supposed to provide same device performance if their physical thickness are not equal but equivalent, called “Equivalent oxide thickness” (EOT). For ultra thin body (UTB) devices like XOI, despite of EOT, conduction band offset (ΔEC) at gate oxide-channel interface dominates the ballistic performance. In case of In0.3Ga0.7Sb XOI nFET using Al2O3 and HfO2 with 0.5 nm EOT, we show the threshold voltage decreases and the subthreshold slope (SS) increases with increase in ΔEC.8th International Conference on Electrical and Computer Engineering (ICECE 2014), Dhaka, Bangladesh; 12/2014