Conference Proceeding

Fabrication technique for arrays of Germanium-on-Nothing nanowires

Dept. of Electr. & Microelectron. Eng., Rochester Inst. of Technol., Rochester, NY, USA
01/2010; DOI:10.1109/ISDRS.2009.5378043 pp.1 - 2 In proceeding of: Semiconductor Device Research Symposium, 2009. ISDRS '09. International
Source: IEEE Xplore

ABSTRACT The authors have presented a CMOS compatible method for the production and incorporation of NW arrays that may be a basis for future NWFETs and other NW based devices. This work also hints to the possibility of incorporating NWs of different semiconductor material onto the same substrate to achieve high performance FETs, LEDs, and other devices. The authors surmise that alternating layers of Ge and Si could produce stacked Ge NWs similar to the Si NW stacks in other work. Finally, the use of chemicals readily available to most fabrication facilities as well as the use of TMAH, to avoid the mobile ion contamination that can plaque other Si etchants, provides for a series of steps that could be incorporated into a CMOS facility.

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Keywords

alternating layers
 
CMOS compatible method
 
CMOS facility
 
devices
 
different semiconductor material
 
fabrication facilities
 
future NWFETs
 
Ge NWs
 
incorporating NWs
 
incorporation
 
mobile ion contamination
 
performance FETs
 
Si
 
Si etchants
 
Si NW stacks
 
TMAH