Geyser-1: A MIPS R3000 CPU core with fine grain runtime power gating
ABSTRACT Geyser-1, a prototype MIPS R3000 CPU with fine grain runtime PG for major computational components in the execution stage is available. Function units such as CLU, shifter, multiplier and divider are power-gated and controlled at runtime such that only the function unit to be used is powered-on to minimize the leakage power. The evaluation results on the real chip reveals that the fine grain runtime PG mechanism works without electric problems. It reduces the leakage power 7% at 25Â°C and 24% at 80Â°C. The evaluation results using benchmark programs show that the power consumption can be reduced from 3% at 25Â°C and 30% at 80Â°C.
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ABSTRACT: Leakage power dissipation becomes a dominant component in operation power in nanometer devices. This paper describes a design methodology to implement runtime power gating in a fine-grained manner. We propose an approach to use sleep signals that are not off-chip but are extracted locally within the design. By utilizing enable signals in a gated clock design, we automatically partition the design into domains. We then choose the domains that will achieve the gain in energy savings by considering dynamic energy overhead due to turning on/off power switches. To help this decision we derive analytical formulas that estimate the break-even point. For the domains chosen, we create power gating structure by adding power switches and generating control logic to the switches. We experimentally built a design flow and evaluated with a synthesizable RTL code for a microprocessor and a 90nm CMOS device model both used in industry. Results from applying to a datapath showed that the break-even point that achieves the gain exists in the number of enables controlling the power switch. By applying the domains controlled by up to 3 enables achieved the active leakage savings by 83% at the area penalty by 20%.Computer Design, 2006. ICCD 2006. International Conference on; 11/2007
Conference Proceeding: A fine-grain dynamic sleep control scheme in MIPS R3000.[show abstract] [hide abstract]
ABSTRACT: A fine-grain dynamic power gating is proposed for saving the leakage power in MIPS R3000 by sleep control and applied to a processor pipeline. An execution unit is divided into four small units: multiplier, divider, shifter and other (CLU). The power of each unit is cut off dynamically, based on the operation. We tape-outed the prototype chip Geyser-0, which provides an R3000 Core with the power reduction technique, 16 KB caches and translation lookaside buffer (TLB) using 90 nm CMOS technology. The evaluation results of four benchmark programs for embedded applications show that 47% of the leakage power is reduced on average with 41% area overhead.26th International Conference on Computer Design, ICCD 2008, 12-15 October 2008, Lake Tahoe, CA, USA, Proceedings; 01/2008
- IEICE Transactions. 01/2005; 88-C:528-535.