NBTI Lifetime Prediction and Kinetics at Operation Bias Based on Ultrafast Pulse Measurement

Abstract

Predicting negative bias temperature instability (NBTI) lifetime can be dangerous since it is difficult to assess its safety margin. The common technique uses gate bias V_g acceleration to reduce the test time, and the data were typically obtained from quasi-DC measurements. Recently, it has been shown that substantial recovery occurs during the quasi-DC measurement, and the suppression of recovery requires using ultrafast pulse measurement, where time was reduced to the order of microseconds. In a real circuit, different transistors have different levels of recovery, and the worst case scenario is when recovery is suppressed. At present, there is little information on how this worst case NBTI lifetime can be predicted and whether the traditional V_g acceleration technique can still be used. This work will show that the prediction based on the V_g acceleration results in a substantial error, and its cause will be analyzed. To predict the worst case lifetime, a model for NBTI kinetics under operation gate bias is developed. This kinetics includes contributions from both as-grown and generated defects, and it no longer follows a simple power law. Based on the new kinetics, a single-test prediction method is proposed, and its safety margin is estimated to be 50%.

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228IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 1, JANUARY 2010
NBTI Lifetime Prediction and Kinetics at Operation
Bias Based on Ultrafast Pulse Measurement
Zhigang Ji, L. Lin, Jian Fu Zhang, Ben Kaczer, and Guido Groeseneken
Abstract—Predicting negative bias temperature instability
(NBTI) lifetime can be dangerous since it is difficult to assess its
safety margin. The common technique uses gate bias Vgaccelera-
tion to reduce the test time, and the data were typically obtained
from quasi-dc measurements. Recently, it has been shown that
substantial recovery occurs during the quasi-dc measurement, and
the suppression of recovery requires using ultrafast pulse mea-
surement,wheretimewasreducedtotheorderofmicroseconds.In
a real circuit, different transistors have different levels of recovery,
and the worst case scenario is when recovery is suppressed. At
present, there is little information on how this worst case NBTI
lifetime can be predicted and whether the traditional Vg accel-
eration technique can still be used. This work will show that the
prediction based on the Vg acceleration results in a substantial
error, and its cause will be analyzed. To predict the worst case
lifetime, a model for NBTI kinetics under operation gate bias is de-
veloped. This kinetics includes contributions from both as-grown
and generated defects, and it no longer follows a simple power
law. Based on the new kinetics, a single-test prediction method is
proposed, and its safety margin is estimated to be 50%.
Index Terms—Bias temperature instability, defects, degrada-
tion, device lifetime prediction, gate dielectrics, MOSFETs, NBTI,
positive charging, reliability.
I. INTRODUCTION
N
and has recently received much attention [1]–[12]. The NBTI
lifetime is typically defined as the time for the threshold
voltage shift ΔVthto reach a preset level [6]–[11]. Under an
operation gate bias Vgop, the required lifetime is ten years,
and the degradation under Vgopcan be too low to reliably be
measured within a practical stress time. To predict the lifetime
under Vgop, multiple accelerated tests are carried out with
stress biases Vgsthigher than Vgop. The accelerated lifetime is
typically fitted with |Vgst|−α[6], [7] or exp(−|Vgst|) [8], [9],
and then extrapolated to Vgop, so that the lifetime under Vgop
can be estimated. Recent works [2]–[5], however, have raised
several questions on the validation of the preceding prediction
technique, as described here.
EGATIVE bias temperature instability (NBTI) is limiting
the lifetime of pMOSFETs with SiON gate dielectric
Manuscript received June 24, 2009; revised September 16, 2009. Current
version published December 23, 2009. The review of this paper was arranged
by Editor J. Suehle.
Z. Ji, L. Lin, and J. F. Zhang are with the School of Engineering, Liverpool
John Moores University, L3 3AF Liverpool, U.K. (e-mail: J.F.Zhang@ljmu.
ac.uk).
B. Kaczer is with the Inter-university MicroElectronics Centre (IMEC), 3001
Leuven, Belgium.
G. Groeseneken is with the IMEC, 3001 Leuven, Belgium, and also with
Katholieke Universiteit Leuven, 3001 Leuven, Belgium.
Digital Object Identifier 10.1109/TED.2009.2037171
First, the aforementioned prediction technique was devel-
oped based on quasi-dc measurements with a measurement
time for transfer characteristics Id–Vgup to seconds [7]–[9],
[12].Recentworks[2]–[5]haveshownthatsubstantialrecovery
occurs during the measurement, and to suppress the recovery,
the measurement time must be reduced to the order of tens
of microseconds by using the ultrafast pulse (UFP) technique
[2], [4], [5], [10]. In a real circuit, different transistors will
experience different levels of recovery, and the worst case
scenario will be no recovery. It is not known whether the
Vgacceleration technique previously described is still applica-
ble in this case.
Second, the threshold voltage is typically evaluated by ex-
trapolating the transfer characteristic Id–Vg, and the sensing Vg
used here is close to Vth. In a practical circuit, the operation
bias is higher than Vth, and an implicit assumption of early
works is that ΔVth is insensitive to the sensing Vg. Recent
work [4], [10], however, shows that ΔVthincreases with the
sensing Vg, and its value at Vgopcan double the level extracted
by extrapolating Id–Vg. There is no information on how the
lifetime can be predicted by including this dependence on the
sensing Vg.
Third, not only recovery but also degradation can occur
during the measurement [4], [5], [10]. In an NBTI test, the first
measured point is used as the reference value [3], [13], and
if the reference is degraded, every subsequent data point will
be affected. For some “on-the-fly” technique recently proposed
[3], [13], the sensing Vg is the stress bias, and it is reported
that substantial degradation can occur for the first point when
measured by a typical quasi-dc parameter analyzer [4], [10].
The lifetime cannot reliably be predicted based on a degraded
reference.
In this paper, we will show that, when the recovery is
suppressed, ΔVthdoes not follow a simple power law against
stresstime,andthekineticsatdifferent Vgst’sarenotinparallel,
making the conventional Vgacceleration technique inapplicable
here. To predict the worst case lifetime, a physics-based NBTI
kinetics at Vgopis proposed, which includes contributions from
both as-grown and generated defects. An effort will be made
to estimate the safety margin of this new lifetime prediction
method.
II. DEVICES AND EXPERIMENTS
A. Devices
To test the applicability of the proposed NBTI kinetics
and lifetime prediction method, samples from six different
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JI et al.: NBTI LIFETIME PREDICTION AND KINETICS AT OPERATION BIAS BASED ON ULTRAFAST PULSE MEASUREMENT229
TABLE I
WAFERS AND THE FITTED PARAMETERS AT 125◦C
processes were used, as shown in Table I. The SiON sam-
ples have p+ poly-si gate; four of them were plasma ni-
trided for different times, and one was thermally nitrided. One
HfSiON/SiON stack was also prepared by atomic layer chemi-
cal vapor deposition (ALCVD) with 80% Hf and a TiN gate.
B. Experiments and Measurements
The typical NBTI test procedure is to stress pMOSFETs
under a constant Vgstand temperature for a prespecified time,
and the degradation was then monitored by interrupting the
stress and measuring Id–Vg[2], [12], [13]. This “stress-then-
sense” procedure is also used for this paper. Since the objective
is to study the NBTI lifetime prediction and kinetics with
recovery suppressed, the UFP Id–Vg is used. Recent works
[2], [4], [10] have shown that recovery during measurement
can effectively be suppressed to within the measurement res-
olution when the pulse edge time was reduced to the order of
tens of microseconds. Both the pulse rise and fall times are
5 μs in this work. The majority of tests were carried out at
125◦C, with a typical test time ranging from microseconds
to 75 h.
We now address the degradation in the reference value. In
early works, the reference value for an NBTI test was typically
obtained by using a quasi-dc parameter analyzer, and the time
for measuring one point trwas 10–150 ms [4], [10]. To show
that this quasi-dc reference is degraded, Fig. 1 compares the
quasi-dc Id–Vgwith the UFP Id–Vgwhen the edge time is 5 μs.
When the sensing Vgis low and around Vth≈ −0.3 ∼ −0.5 V,
Iddegrades little, and the quasi-dc value can be used as the
reference. At |Vgop| = 1.2 V, however, the degradation of the
quasi-dc reference becomes observable. Moreover, some on-
the-fly technique [3], [13] uses stress bias |Vgst| > |Vgop| as the
sensing Vg, and Fig. 1 shows that the quasi-dc reference further
degrades for higher |Vg|.
To show that the Idat Vgop= −1.2 V degrades little when
measuredwithapulseedgeof5μs,Fig.2(a)givestheId,which
isrepeatedlymeasured30times.Degradationwasnotobserved,
and a measurement resolution of ±0.23% was achieved.
In this paper, we intend to stress the device at |Vgop| = 1.2 V,
which is lower than the typical stress bias used in early NBTI
Fig. 1.
on fresh devices. The edge time of the pulse is 5 μs, and it took 150 ms
for recording one point for the quasi-dc technique. Although the degradation
is negligible near the threshold voltage Vth(ex), it increases and becomes
observable at |Vgop| = −1.2 V for the quasi-dc measurement. Therefore, the
quasi-dc Idat |Vgop| = −1.2 V should not be used as the reference value.
tests [2]–[5], [10]. For low degradation, noises must be mini-
mized. The typical commercial parameter analyzers minimize
noises by repeating Id measurement for a given bias many
times and then use their average value. For a stress time of less
than 1 s, we also repeated the pulse measurement many times
(i.e., 30) and used their average value, as shown in Fig. 2(b).
For stress longer than 1 s, we used a quasi-dc parameter
analyzer that automatically uses average values. As will be
shown in Sections III-C and III-D, the measurement accuracy
achieved in this way is good enough to establish a kinetic
model that allows lifetime to be predicted with a safety margin
of 50%.
Comparison of Id–Vg measured by UFP and quasi-dc techniques
C. ΔVthExtraction at the Operation Gate Bias
Traditionally, NBTI-induced ΔVthwas evaluated by extrap-
olating Id–Vg, as shown in the inset of Fig. 3(a), and the
assumption is that ΔVthis insensitive to the sensing Vg. Our
recent work [4], [10], however, shows that |ΔVth| substantially
increases for higher sensing |Vg|. Since measuring ΔVth at
differentsensingVg’sisrarelyreported inthepast,adescription
is given here.
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230 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 1, JANUARY 2010
Fig. 2.
−1.2 V was measured 30 times from the pulsed Id–Vg with an edge time of
5 μs. A measurement resolution of ±0.23% was achieved, and Iddegradation
during the measurement cannot be observed within this resolution. (b) The
pulse measurement (symbol ‘?’) was repeated 30 times for a stress time of
less than 1 s, and the average value (symbol ‘◦’) was used to minimize the
noise. For stress longer than 1 s, we used a quasi-dc parameter analyzer that
automatically used the average value (symbol ‘×’).
Fig. 3(a) shows that the drain current degradation ΔId at
a given sensing Vg can be measured, and the ΔVth can be
evaluated by
Measurement resolution and minimization of noises. (a) Idat Vg =
ΔVth≈
N
?
i=1
ΔVth(i) = −
N
?
i=1
ΔId(i)
[Gm(i) + Gm(i − 1)]/2
(1)
where i and (i − 1) represents two measurement points, and
ΔVth(i) is the incremental degradation between these two
points. Gm is the transconductance and is evaluated from
Id–Vgby
Gm=
dId
d(Vg− Vth).
(2)
d(Vg− Vth) is used in the denominator of the preceding for-
mula since Idis driven by (Vg− Vth) and Vthvaries with Vg
here [4], [10]. A typical result is given in Fig. 3(b), and |ΔVth|
at the operation Vgop= −1.2 V is much higher than |ΔVth|
obtained by extrapolating Id–Vg. Since the objective of this
work is to investigate the worst case NBTI lifetime and kinetics,
we use ΔVthat Vgophereinafter, unless otherwise specified.
Fig. 2(b) shows that |ΔVth| becomes higher than 10 mV
in less than 1 ms under Vg= −1.2 V. This rapid increase in
|ΔVth| does not mean that the quality of the samples used here
is poor [10]. It is caused partially by suppressing recovery with
Fig. 3.
(a) Id–Vg at two stress time points, i.e., (i − 1) for 1 s and i for 1000 s,
which were measured by the UFP technique with an edge time of 5 μs. ΔId
representstheNBTI-inducedcurrentdegradationbetweenthesetwotimepoints
at a given sensing Vg. The inset shows the evaluation of the threshold voltage
shiftbyextrapolatingId–Vg.(b)|ΔVth|increaseswiththesensing|Vg|,sothat
|ΔVth| at |Vgop| = 1.2 V is substantially higher than the |ΔVth(ex)| obtained
by extrapolation.
Evaluation of the threshold voltage shift at different sensing Vg’s.
the pulse measurement and partially by using |Vg| = 1.2 V as
the sensing bias, rather than the conventional extrapolation to
|Vth| ∼ 0.4 V, as shown in our early works [4], [10].
III. RESULTS AND DISCUSSION
A. Inapplicability of the VgAcceleration Prediction Technique
Fig. 4(a)–(c) shows the common procedure for predicting
lifetime: Multiple Vgaccelerated tests were carried out, and the
lifetime τ at Vgopwas estimated by an extrapolation against
Vgst. Vgacceleration is used to allow obtaining a reliable NBTI
kinetics within a practical length of stress time. The safety
margin of the prediction, however, is generally not known.
To assess the prediction safety margin, it is essential to be
able to directly measure ΔVthat Vgst= Vgop. As Vgopdoes
not proportionally reduce with the SiON thickness, the oxide
field during device operation has increased to such a level that
Fig. 4(a) shows that the ΔVth at Vgop= −1.2 V can now
reliably be measured. This allows comparing the measured
stress time for ΔVthto reach a given level under Vgst= Vgop
with that predicted by using Vgacceleration, so that the safety
margin of prediction can be estimated.
In Fig. 4(a), the last measured |ΔVth| reached 60 mV under
Vgst= Vgop, and if we use |ΔVth| = 60 mV to define lifetime,
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JI et al.: NBTI LIFETIME PREDICTION AND KINETICS AT OPERATION BIAS BASED ON ULTRAFAST PULSE MEASUREMENT 231
Fig. 4.
lifetime at Vgop= −1.2 V measured by the UFP technique. (a) Dynamic
behavior of |ΔVth| under different stress biases Vgst is compared, and the
kinetics does not follow a simple power law. The horizontal dashed line
represents |ΔVth| = 60 mV that is used to define the lifetime. (b) and
(c) Measured lifetime is compared with the predicted one based on |Vgst|−α
and exp(−|Vgst|), respectively. The symbol ‘•’ represents the measured
lifetime under |Vgst| = 1.2 V. The solid line was obtained by fitting the data at
higher |Vgst|. The error in prediction is substantial.
Inapplicability of the Vg acceleration technique for predicting NBTI
the stress time for this last point will be the lifetime under
Vgop= −1.2 V. This measured lifetime is compared to the
prediction based on the Vg acceleration in Fig. 4(b) and (c).
Two popular Vg acceleration methods have been used in the
literature: |Vgst|−α[6], [7] and exp(−|Vgst|) [8], [9]. Fig. 4(b)
and (c) shows that there is a substantial difference between the
predicted and measured time, and therefore, Vg acceleration
cannot be used to predict lifetime in our case.
To analyze the reason for the inapplicability of the Vgaccel-
eration technique, we will use the |Vgst|−αacceleration as an
example. The |Vgst|−αacceleration requires
|ΔVth| = B|Vgst|mtn
where B is a constant for a given temperature. At a device
lifetime of t = τ, ΔVth reaches the specified ΔVth(τ), and
we have
?|ΔVth(τ)|
Equations (3) and (4) require the log|ΔVth| ∼ log(t) being
shifted in parallel for different Vgst’s and the power factor
against time n, being insensitive to Vgst, so that log(τ) is
a straight line against log(|Vgst|). For the conventional ΔVth
measured by extrapolating the quasi-dc Id–Vg, Fig. 5(a) and (b)
shows that these requirements can be met, so that the prediction
agrees well with measurement in Fig. 5(c). Once the recovery
is suppressed and Vgop= −1.2 V is used as the sensing Vg,
however, ΔVthin Fig. 4(a) no longer follows a simple power
law, and log|ΔVth| ∼ log(t) at different Vgst’s is generally not
aparallelshift.Aclearexample forthenonparallelshiftisgiven
in Fig. 6. The Vgst effect can no longer be separated into a
“prefactor” like that in (3), and this explains the inapplicability
of the Vgacceleration technique to the case where recovery is
suppressed.
(3)
log(τ) =1
nlog
B
?
−m
nlog(|Vgst|).
(4)
B. NBTI Kinetics at the Operation Gate Bias Based
on the UFP Measurement
Since ΔVth does not follow a simple power law against
stress time when recovery is suppressed, efforts should be made
to develop a model that can describe its dynamic behavior.
For the ΔVthunder Vgst= Vgop= −1.2 V, Fig. 7 shows that
an outstanding feature of the kinetics is the presence of a
“shoulder.” This indicates that there is an initial period when
as-grown defects dominate, and the saturation of their charging
results in the “shoulder.” At longer stress time, generation of
new defects becomes increasingly important and is responsible
for the rise above the “shoulder.”
To support the aforementioned suggestion, two tests were
carriedout.Inthefirsttest,wecheckedtheeffectoftemperature
on the shoulder height. The saturation level of as-grown defects
should be insensitive to temperature [14], [15], and if it domi-
nates the shoulder, the shoulder height should be insensitive to
temperature. This is confirmed by Fig. 8. Fig. 8 also shows that
the rise above the shoulder is thermally activated, supporting
that defect generation is thermally accelerated.
In the second test, we compare the charging and discharg-
ing rates of the defect responsible for the shoulder. Early
works [15]–[18] identified three different types of positive
charges in the dielectric, i.e., antineutralization positive charges
(ANPCs), cyclic positive charges (CPCs), and as-grown hole
traps (AHTs), as illustrated by Fig. 9. ANPC has an energy
level above the bottom edge of silicon conduction band Ec,
making its discharging more difficult than charging. CPC has
an energy level close to Ec, and its charging rate is similar to the
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232IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 1, JANUARY 2010
Fig. 5.
tional ΔVth(dc-ex) measured by extrapolating the quasi-dc Id–Vg. (a) ΔVth
(dc-ex) follows the power law. The horizontal dashed line represents |ΔVth| =
19 mV that is used to define the lifetime. (b) Power factor is insensitive to the
stress bias. The solid line represents the average power factor of n = 0.1926.
(c) Prediction (solid line) agrees with the measurement (symbol ‘•’).
Lifetime prediction by the Vg acceleration technique for the conven-
discharging rate. In contrast, AHT is below the top edge of the
silicon valence band, and there are far more valence electrons
for discharging than hot holes required for charging. As a result,
AHT has the signature that discharging is much faster than
charging. Fig. 10 shows that, when the stress time corresponds
to the shoulder, the charging and discharging properties of the
defect agree with the signature of AHT, supporting that AHT
dominates the shoulder.
We now discuss how hot holes can be generated under a
modest bias of Vgop= −1.2 V. Hot holes can come from
three sources: First, the surface quantization effect gives energy
Fig. 6.
ΔVthsensed at |Vg| = 1.2 V. The dashed curve was obtained by shifting the
symbol ‘×’ downward in parallel.
Kinetics at different Vgst’s is not shifted in parallel for the UFP
Fig.7.
By combining the first-order model for AHTs with the power law for defect
generation, ΔVthcan be fitted over ten orders of magnitude in time, as shown
by the solid line. The dashed lines show that ΔVthis initially dominated by
AHTs, but the generated defects become important at longer stress time.
KineticfeatureoftheUFPΔVthsensedat|Vg| = 1.2V:a“shoulder.”
Fig. 8.
insensitive to temperature, but the generation of defects above the shoulder is
thermally accelerated.
Effect of temperature on NBTI kinetics. The height of the shoulder is
subbands [19], [20]. Although the hole density reduces as
the energy increases, there are holes in the higher subbands.
Second, process “a” in Fig. 11 shows that an electron tunneling
from the gate can recombine with a hole in the substrate, and
the released energy can create hot holes [21]. Third, it has
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JI et al.: NBTI LIFETIME PREDICTION AND KINETICS AT OPERATION BIAS BASED ON ULTRAFAST PULSE MEASUREMENT233
Fig. 9.
ANPCs have an energy level above the bottom edge of the silicon conduction
band Ec, making them difficult to neutralize. The CPCs have an energy level
near Ec, resulting in similar charging and discharging rates. The AHTs have an
energy level below the top edge of the silicon valence band Ev. Their charging
requires hot holes, leading to charging that is slower than discharging.
Energy band diagram of different types of positive charges. The
Fig. 10.
defects. The stress time is 2.6 s, which corresponds to the region where as-
grown defects dominate. The discharging under Vg > 0 is much faster than the
charging under Vg < 0, which is a unique signature of AHTs. The solid lines
are guides for the eye. It should be noted that the rapid discharging within 5 μs
observedherewasachievedbyapplyingapositivegatebias.ForanormalNBTI
test, however, positive gate bias was not applied, and the AHT discharging at
Vg = −1.2 V within 5 μs was negligible [4], [10].
Comparison of the charging and discharging rates for the as-grown
Fig. 11.
under Vg = −1.2 V. Process “a” shows that the energy released by the
electron–hole recombination in the substrate can create hot holes. Process “b”
shows that the photons emitted from the gate can be absorbed to generate hot
holes.
Schematic showing the physical processes for generating hot holes
been proposed that photons can be emitted by electron–hole
recombination in the gate [22], as illustrated by process “b” in
Fig. 11. Holes can become hot by absorbing the photons.
On the kinetics, the charging of AHT generally follows the
first-order reaction model [23], [24], whereas the generation of
Fig.12.
are test data, but only symbol “×” was used for fitting with a power law in
the range of 26.8 s < t < 2680 s. The thick dashed line is extrapolated from
the fitted line for prediction. τm is the time for the last test point, and τp
is the predicted time. τ is overestimated by a factor of 75000.
Lifetimeprediction based on themethodproposedin [5].All symbols
Fig. 13.
bols are test data, but only symbol “×” was used for fitting. ΔVth(t) − ΔVth
(1 s) (symbol “+”) was fitted with a power law, and ΔVth(1 s) was then added
back. The dashed line is extrapolated for prediction. τmis the time for the last
test point, and τp is the predicted time. This method underestimates τ by a
factor of 10.
Lifetime prediction based on the method proposed in [27]. All sym-
Fig. 14.
same as those in Figs. 12 and 13, and only symbol “×” was used for fitting.
Our model substantially reduces the prediction error, and τp/τm= 1.03. The
test sample is a plasma-nitrided 1.85-nm SiON.
Lifetime prediction based on our model: (5). The test data are the
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234IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 1, JANUARY 2010
Fig. 15.
(c) 2.0-nm 45-s plasma SiON. (d) 2.0-nm 20-s plasma SiON. (e) 2.0-nm/1.0-nm HfSiON/SiON stack prepared by ALCVD with TiN gate. The safety margin for
the prediction is within 50% in all cases.
Applicability of the single-test lifetime prediction technique for different fabrication processes. (a) 1.4-nm plasma SiON. (b) 2.7-nm thermal SiON.
new defects follows a power law [5], [6], [25]. By combining
these two, we have
ΔVth= Atn+ c(1 − e−t/t∗).
(5)
For a given stress temperature and bias, A, n, c, and t∗are
constants and were obtained by fitting test data with the least-
square errors, and their values are given in Table I. There is
only one n for the whole stress period, and this n is not the
slope of the data in Fig. 7, i.e., n ?= d(log|ΔVth|)/d[log(t)].
Fig. 7 shows that (5) can model the “shoulder,” and this simple
physics-based model can fit the ΔVthover ten orders of stress
time. The two dashed lines represent the contribution from
AHT and generated defects, respectively. AHT clearly domi-
nates initially, but generated defects become more important for
longer stress time. On the nature of degraded defects, our early
works [12], [13], [15]–[18], [23], [24] show that both interface
states and new hole traps are created by stresses. The new hole
traps are further separated into ANPCs and CPCs, each with
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JI et al.: NBTI LIFETIME PREDICTION AND KINETICS AT OPERATION BIAS BASED ON ULTRAFAST PULSE MEASUREMENT235
unique signatures. A detailed discussion, however, is out of the
scope of this work.
C. Lifetime Prediction Based on a Single Test
The Vgacceleration technique was developed for predicting
the lifetime caused by time-dependent dielectric breakdown
(TDDB) [26]. For TDDB, intrinsic dielectric breakdown gen-
erally does not occur within an affordable test time under the
operation bias, and multiple Vg accelerated tests are essen-
tial. For NBTI with a sensing |Vg| = 1.2 V based on UFP
measurement, we have shown that the prediction based on Vg
acceleration is inapplicable, and an obvious question is how to
assess lifetime in this case. One possibility is to use thermal
acceleration. Fig. 8, however, shows that log|ΔVth| at different
temperatures is not shifted in parallel, so that it does not offer
a reliable prediction method. Since ΔVth can be measured
at Vgop (Fig. 7), in principle, lifetime can be estimated by
extrapolating the ΔVthagainst stress time based on a single
test at Vgop. This requires a reliable kinetic model that can not
only fit the existing test data but also predict the future.
The affordable test time is typically on the order of days, and
the data were used to predict lifetime in years, so that a kinetic
model should have the ability to predict at least two decades
ahead. To test the prediction ability of a model, the test data
in the last two decades are not used for fitting the model, the
ΔVthat the last test point is considered as ΔVth(τ), and the
time for the last point is treated as the measured lifetime τm,
although τmis not the real device lifetime. The departure of
kinetics from a simple power law was noted in the past, and
suggestions were made on how the lifetime prediction method
should be modified to take this departure into account [5], [27].
One proposed method is only using the data with a stress time
of more than 10 s to fit the power law against time [5], but there
is no information on the prediction accuracy. Fig. 12 shows that
this method can overestimate τ by a factor of 75000. Another
proposed method is to fit ΔVth(t) − ΔVth(1 s) with a power
law [27], but Fig. 13 shows that it underestimates τ by a factor
of 10. By applying our model of (5) to the same set of data,
Fig. 14 shows that good agreement is achieved between the
measurement and the prediction with τp/τm= 1.03.
D. Applicability of the Single-Test Prediction Method
for Different Processes
Although a good prediction is achieved in Fig. 14, it is
inadequate to demonstrate that a prediction method works for
one process. For a prediction technique to be useful, it must be
applicable to samples fabricated by a wide range of processes.
We now test its applicability for four other SiON layers with
different nitrogen concentrations and nitrided either by plasma
or thermally. Moreover, an ALCVD HfSiON/SiON stack is also
tested, and the thickness of these samples is given in Table I.
Fig.15(a)–(e)showsthatΔVthfollows(5)inallcases,although
the “shoulder” in some samples is less apparent. The prediction
achieved a safety margin of 50% or less in all the processes
tested, making us confident that the single-test technique is
generally applicable.
Table I shows that the fitted power factors for different
processes have a range of 0.07–0.36, which agrees with the
range reported by early works [28]–[34]. Early works reported
that the variation of power factor could come from two sources,
i.e., different hydrogenous species and different nitrogen den-
sities and distributions. On the hydrogenous species, it was
reported that the power factor for H+[32], atomic hydrogen
[33], and H2[34] is 0.5, 0.25, and 0.16, respectively. On the
nitridation effect, it was reported that an increase in nitrogen
reduces the power factor [28], [29]. Moreover, for the same area
density of nitrogen, the power factor of a thermally nitrided
SiON is typically lower than that of a plasma-nitrided SiON
[28]. The power factor in Table I agrees with these trends.
Sample A has the lowest nitrogen density and the highest power
factor. Sample C was thermally nitrided and has the lowest
power factor.
IV. CONCLUSION
This work has investigated the NBTI lifetime prediction in
the worst case scenario where the recovery is suppressed and
ΔVth is sensed at the operation gate bias. In this case, the
conventional Vgaccelerationpredictionisinapplicable,because
the NBTI kinetics no longer follow a simple power law, and
an increase in stress bias does not lead to a parallel shift of
log|ΔVth|.
To predict the lifetime at the operation gate bias based on the
UFP measurement, NBTI kinetics and defects are examined.
An outstanding feature of the kinetics is the presence of a
“shoulder,” which is insensitive to temperature and must be
dominated by the charging of as-grown defects. The charging
and discharging properties of the defect agree well with the
signature of AHTs. By combining the first-order model for the
AHTs and the power law for generating new defects, ΔVthcan
be modeled over ten orders of stress time. This kinetic model
is then used to predict the NBTI lifetime, based on a single
test at the operation temperature and bias. For the six different
processes tested, the safety margin of the single-test prediction
technique is within 50%, which is substantially better than the
methods proposed in early works.
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Zhigang Ji received the B.Eng. degree in electric en-
gineering from Tsinghua University, Beijing, China,
in 2003 and the M.Eng. degree in microelectronics
from Peking University, Beijing, in 2006. He is cur-
rently working toward the Ph.D. degree in the Reli-
ability Laboratory, School of Engineering, Liverpool
John Moores University, Liverpool, U.K.
He is focusing on semiconductor device relia-
bility issues, particularly negative bias temperature
instability and the new measurement techniques for
characterizing nano-CMOS devices.
L. Lin received the B.Sc. degree in electronic engi-
neering from the University of Central Lancashire,
Preston, U.K., in 2001 and the M.Sc. degree in
microelectronics system design from Liverpool John
Moores University, Liverpool, U.K., in 2003. He
is currently working toward the Ph.D. degree in
the Reliability Laboratory, School of Engineering,
Liverpool John Moores University.
He is focusing on semiconductor device reliability
issues, particularly negative bias temperature insta-
bility and new measurement techniques for charac-
terizing nano-CMOS devices.
Jian Fu Zhang received the B.Eng. degree in elec-
trical engineering from Xi’an Jiao Tong University,
Xi’an, China, in 1982 and the Ph.D. degree in elec-
trical engineering from the University of Liverpool,
Liverpool, U.K., in 1987.
From 1986 to 1992, he was a Senior Research
Assistant with the University of Liverpool, where
he worked on the dielectric recovery of plasma in
accelerating gas flow, plasma processing of semi-
conductors, and reliability of MOS devices. In 1992,
he joined the School of Engineering, Liverpool John
Moores University, Liverpool, U.K., as a Senior Lecturer. He became a Reader
in Microelectronics in 1996 and a Professor in 2001. He has authored or
coauthored more than 100 journal and conference proceeding papers, including
ten invited papers at several international conferences. His current research
interests include the performance, degradation, and defect characterization of
MOSFETs and nonvolatile memories.
Dr. Zhang was a member of the technical program committee for the IEEE
Semiconductor Interface Specialists Conference (SISC).
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JI et al.: NBTI LIFETIME PREDICTION AND KINETICS AT OPERATION BIAS BASED ON ULTRAFAST PULSE MEASUREMENT237
Ben Kaczer received the M.S. degree in physical
electronics from Charles University, Prague, Czech
Republic, in 1992 and the M.S. and Ph.D. degrees in
physics from The Ohio State University, Columbus,
in 1996 and 1998, respectively.
In 1998, he joined the Reliability Group of the
Inter-university MicroElectronics Centre (IMEC),
Leuven, Belgium, where his activities have included
research on the degradation phenomena and relia-
bility assessment of SiO2, SiON, high-k, and fer-
roelectric films; planar and multiple-gate FETs and
circuits; and characterization of Ge/III-V and MIM devices. He has authored
or coauthored more than 200 journal and conference proceeding papers, and
presented eight invited presentations and three International Reliability Physics
Symposium (IRPS) tutorials.
Dr. Kaczer has served or is serving in various functions at the IEEE Inter-
national Electron Device Meeting, IRPS, International Integrated Reliability
Workshop, IEEE Semiconductor Interface Specialists Conference, and Insu-
lating Films on Semiconductor conference. He received the OSU Presidential
Fellowship and support from Texas Instruments, Inc., Dallas, for his Ph.D.
research on the ballistic-electron emission microscopy of SiO2and SiC films.
He was the recipient of the Best and the Outstanding Paper Awards at IRPS
and the Best Paper Award at the International Symposium on the Physical and
Failure Analysis of Integrated Circuits.
Guido Groeseneken received the M.Sc. degree in
electrical and mechanical engineering and the Ph.D.
degree in applied sciences from Katholieke Univer-
siteit Leuven (KU Leuven), Leuven, Belgium, in
1980 and 1986, respectively.
In 1987, he joined the R&D Laboratory, Interuni-
versity Microelectronics Center (IMEC), Leuven,
where he is responsible for research in reliability
physics for deep-submicrometer CMOS technolo-
gies. From October 2005 to April 2007, he was also
responsible for the IMEC Post-CMOS Nanotech-
nology Program within IMEC’s core partner research program. Since 2001,
he has been a Professor with KU Leuven, where he is also the Program
Director of the Master in Nanoscience and Nanotechnology and is also co-
ordinating a European Erasmus Mundus Master Program in nanoscience and
nanotechnology. He has authored or coauthored more than 500 publications in
international scientific journals and international conference proceedings, and
six book chapters. He is the holder of ten patents in his fields of expertise.
He has made contributions to the fields of nonvolatile semiconductor memory
devices and technology, reliability physics of VLSI technology, hot carrier
effects in MOSFET’s, TDDB of oxides, negative-bias-temperature instability
effects, ESD protection and testing, plasma-processing-induced damage, elec-
trical characterization of semiconductors, and characterization and reliability of
high-k dielectrics. His current research interests include nanotechnology for
post-CMOS applications, such as carbon nanotubes for interconnect applica-
tions and tunnel FETs for alternative nanowire devices.
Dr. Groeseneken became an IMEC Fellow in 2007. He has served as
technical program committee member of several international scientific con-
ferences, among which are the IEEE International Electron Device Meeting
(IEDM), the European Solid-State Device Research Conference (ESSDERC),
the International Reliability Physics Symposium, the IEEE Semiconductor
Interface Specialists Conference (SISC), and the EOS/ESD Symposium. From
2000 to 2002, he was the European Arrangements Chair of IEDM. In 2005,
he was the General Chair of the Insulating Films on Semiconductor (INFOS)
conference, which was organized in Leuven, Belgium.
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