Among the 3 types of polyimide (PI) systems, pre-imidized,
polyamic ester and polyamic acid, the latter has been shown to react
with Cu surfaces when it is spun coated. This paper reviews Cu-polyimide
adhesion and diffusion data and present various wet process alternatives
to minimize Cu diffusion into poly(biphenyl dianhydride-p-phenylene
diamine) (BPDA-PDA) polyamic acid precursor. Two different process
options were investigated: a precoat or adhesion promoters (A1100, AP420
and benzotriazole) prior to the polyamic acid apply, and an additive
(Tetrazole or BTA) formulated in the PAA solution. The 5 processes were
compared with respect to adhesion, capacitance, dielectric constant and
reliability. Only the BTA formulation had adhesion problems which were
attributed to the A1100 precoat used. A1100 as a precoat was further
evaluated on various copper surfaces and curing environments. All
proposed solutions performed well when used on a MCM-D/C module which
was used to extract electrical parametrics and was further subjected to
"Therefore, if even only one of the solder joints was the weakest part within the die, it would cause the sample to fail after temperature cycling testing with daisy chain design. Polyimide is a material usually used in chip scale packaging as the insulting layer for metal traces.So, most of them were added with a promoter to enhance the adhesion strength between the metal traces and itself . Therefore, a weak adhesion strength between metal thin film and polyimide could be obtained by removing the promoter in the application for the bottom insulating layer (BIL) of RDL or the top layer of silicon chip. "
[Show abstract][Hide abstract] ABSTRACT: Wafer level chip scale packaging (WLCSP) has some advantages, such as real die size packaging, high electrical performance, and low manufacturing cost. However, because the mechanical reliability of a large die can not be guaranteed due to the coefficient of thermal expansion (CTE) mismatch between silicon and organic printed circuit board (PCB), WLCSP technology is still not fully accepted. We have developed a new solder joint protection-WLCSP (SJP-WLCSP) structure with a delamination layer interposed between the top layer of the chip and the bottom insulating layer of the metal redistribution traces. The stress on the solder joints can be released by the cracks forming in the delamination layer, which protects the solder joints from cracking. Since the cracking of the delamination layer is irrelevant to the electrical circuits of the packaging, the packaged integrated circuits (IC) device remains functional. One of the possibilities for processing the SJP-WLCSP was implemented and validated successfully in the SiLK-wafer samples. The board level packaging samples, using the daisy chain resistance measurement passed 1000 cycles of the temperature cycling testing.
[Show abstract][Hide abstract] ABSTRACT: The G5, the most recent member of the S390 server family, was
announced in May 1998. The multichip module (MCM) at the heart of the G5
system consists of 29 CMOS chips on a 127.5 mm glass ceramic substrate
with 6 levels of thin films (TF) including 1 signal plane pair. System
performance of the G5 exceeds 1000 MIPS. This breakthrough performance
resulted from the synergy created by combining IBM's leadership
technologies in CMOS high frequency microprocessor design with advanced
packaging and flip chip interconnections. From a substrate perspective.
IBM moved from alumina ceramic with molybdenum (Mo) conductor to
cordurite/glass ceramic, and copper (Cu) conductor, and from TF
redistribution (4 levels) to TF wiring (6 levels). This paper discusses
the TF implications from a change of substrate material and increased
wiring density, as well as the need to implement a polyimide cushion
layer as part of a pin grid array (PGA) fabrication process that
supports 4224 I/O's
[Show abstract][Hide abstract] ABSTRACT: As WLCSP packaging technology travels the road to ubiquity a transition is unfolding. WLCSP designs and material selection paradigms are moving from a process integration focus to one of product integration. The transition is driven by the application of WLCSP technology to larger die and enabled by the improvement in materials properties and process requirements. Both the driver and the enabler are consequences of the relentless pressure on cost that is the hallmark of the recent industry cycle. Achieving the goal of a low cost, high reliability, product-driven package solution required the balancing a variety of needs and characteristics. Often these are in conflict and detente is needed to ease the tension. The design goals of a Hi Rel WLCSP must provide superior protection, mechanical strength and electrical contact. A successful solution necessitated the need to avoid special tools or processes. The solution also needed to exceed the reliability requirements of the end customer. A key component of the WLCSP structure is the dielectric which is interposed between the solder bumps and the die. It must provide most of the protection functions while supporting the bumps and buffering the bump strains. A negative tone, photosensitive polyimide was ultimately selected. This polymer was designed with the goal of achieving thermal and mechanical cured film properties fully compatible with the stresses and thermal excursions associated with WLP thin-film processing and bumping. Integration of the new polymer require careful characterization and process optimization to assure critical material qualities such adhesion were achieved. Similar optimizations were run for assembly operations. Based on test results described herein, a double-layer polyimide, copper redistributed, eutectic SnPb or Pb-free bumped WLCSP was developed that exceeded all the design goals. Salient differentiators of the WLCSP solution are identified. Improved reliability was achieved, and new design standards were established relative to RF capability and power density.
Electronic Components and Technology Conference, 2004. Proceedings. 54th; 07/2004
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