Optimization of the integrator output swing in low-voltage sigma-delta modulators

Abstract

This paper presents a technique which allows us to limit to 0.5
times the reference voltage the output swing of the first integrator in
a sigma-delta (ΣΔ) modulator. The conventional
ΣΔ modulator architecture is modified by replacing the
global feedback path to the input of the first integrator with a local
feedback. The overall performances of the modulator are maintained by
restoring at the output of the first integrator the global feedback
information by means of a simple additional circuit. The simulation and
the experimental results obtained from a prototype implementing a
second-order ΣΔ modulator validate the proposed approach

Full text

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OPTIMIZATION OF THE INTEGRATOR OUTPUT SWING IN LOW-
VOLTAGE SIGMA-DELTA MODULATORS
Pier0 Maleovati(') and Franco Malaberti"? 2,
Department of Electrical Engineering, University of Pavia
Via Ferrata 1, 27 100 Pavia, Italy
Tel. +39 0382 505205, Fax. +39 0382 505677
E-Mail: piero@ele.unipv.it
(21 Department of Electrical Engineering, Texas A&M University
Analog and Mixed-Signal Center, College Station, TX 77843-3 128, USA
Tel. +1 979 8457160, Fax. +1979 8457161
E-Mail: franco@ee.tamu.edu
ABSTRACT
This paper presents a technique which allows us to limit to
0.5 times the reference voltage the output swing of the first
integrator in a sigma-delta (CA) modulator. The convention-
al XA modulator architecture is modified by replacing the
global feedback path to the input of the first integrator with
a local feedback. The overall performances of the modula-
tor are maintained by restoring at the output of the first in-
tegrator the global feedback information by means of a
simple additional circuit. The simulation and the experi-
mental results obtained from a prototype implementing a
second-order EA modulator validate the proposed approach.
1. INTRODUCTION
Sigma-Delta (CA) modulators are the most suitable A D
converters for low-frequency, high-resolution applications,
in view of their inherent linearity, reduced anti-aliasing fil-
tering requirements and robust analog implementation.
Moreover, by trading accuracy with speed, CA modulators
allow high performance to be achieved with low sensitivity
to analog component imperfections and without requiring
component trimming.
However. the reduction of the available power supply volt-
ages, due to the reduced gate oxide thickness and the re-
quest for low-power consumption in digital and mixed
analog-digital integrated circuits, introduces severe con-
straints in the design of EA modulators. In particular, the
available voltage swing at the output of the integrators de-
creases with the supply voltage, thus leading to a strong
degradation of the useful dynamic range. In a conventional
single-bit second-order CA modulator, for example. a volt-
age swing as large as 1.5 times the reference voltage used
(i. e. the input signal full scale) is required to avoid a signif-
icant performance degradation. With low power supply
voltages (e. g. 1.8 V or even 1 V), therefore, the maximum
possible reference voltage and hence the maximum signal-
to-noise ratio (SNR) achievable becomes quite small. To
overcome this limitation two possible approaches can be
adopted: using rail-to-rail analog building blocks or im-
proving the ZA modulator architecture.
Obviously, the use of rail-to-rail operational amplifiers
leads to a corresponding improvement in the maximum ref-
erence voltage. However, operational amplifiers with an ex-
tended output swing operated with low power supply
voltage [ 11 typically require additional circuitry, thus in-
creasing the circuit complexity and the power consumption.
Moreover, even in the best case, the maximum reference
voltage for a second-order XA modulator is limited to two
thirds of the power supply voltage. Scaling the first integra-
tor gain leads also to a reduction of the required operational
amplifier output swing. However, this is not feasible in
those applications where thermal noise (kT/ C noise) and
speed are dominant constraints, since the reduction of the
integrator gain has to be achieved by reducing the sampling
capacitance (the kT / C noise increases) or by increasing the
feedback capacitance (the operational amplifier load in-
creases).
By contrast, by modifying the architecture of the CA modu-
lator as proposed in this paper, the maximum reference volt-
age in the second-order case can be increased to twice the
operational amplifier output swing with a small amount of
additional circuitry. The proposed technique, implemented
in this paper on a second-order CA modulator, can be easily
extended to higher order loops.
2. ZA MODULATOR ARCHITECTURE
The block diagram of a conventional second-order ZA mod-
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ulator is shown in Fig. 1. The circuit consists of two analog
integrators and a comparator. Among the different architec-
tures available so far for implementing second-order XA
modulators, the solution shown in Fig. 1 requires the lowest
integrator output swing (1.5 times the reference voltage
Vref) PI-
0s
Figure 1. Block diagram of a conventional second-order
U modulator
Fig. 2 shows the block diagram of the solution proposed in
this paper. In order to reduce the output swing of the first in-
tegrator we eliminate the feedback path from the output
(BS) to the input of the modulator. Instead, we use a local
feedback which monitors the signs of input signal and of the
first integrator output by means of two comparators, using
this information to subtract the reference voltage from the
input signal if both signs are positive or add the reference
voltage to the input signal if both signs are negative (signal
FF). The effect of this operation is obviously a strong re-
duction of the output swing required in the first integrator,
but the overall modulator behaves differently (i. e. we ob-
tain a different bitstream at the output). To maintain the per-
formance unchanged, we need to restore at the output of the
first integrator the information that we lost by removing the
feedback path from the input to the output of the modulator.
1-
I
Figure 2. Block diagram of the proposed second-order
ZA modulator
This operation is performed in the digital domain by inte-
grating the difference between FF and BS and adding the re-
sult to the output of the first integrator by means of a
suitable digital-to-analog converter (DAC). With this pro-
cedure the input signal of the second integrator and conse-
quently the output signal BS are exactly the same that we
would obtain in a conventional second-order XA modulator,
thus maintaining the performance unaltered. The output
swing of the first integrator, however, is strongly reduced.
The additional hardware required to achieve this result is
limited to two comparators, a digital integrator and a low-
resolution DAC. The effect of any non-idealities in the
DAC on the XA modulator performance is negligible, be-
cause of the large gain of the first integrator. The output
swing of the second integrator is usually not important, be-
cause it can be optimized by adjusting the integrator gain.
The comparator indeed is only sensitive to the sign of its in-
put signal and hence the amplitude of the second integrator
output signal does not affect the modulator performance.
We verified the proposed ZA modulator architecture with
behavioral simulations. The histograms of the first integra-
tor output voltage in the conventional and the proposed XA
modulators are reported in Fig. 3. The first integrator output
swing in the conventional modulator is 1.5 times the refer-
ence voltage as expected, while in the proposed modulator
it is reduced to only 0.5 times the reference voltage. This ef-
fect can be intuitively explained by the level shifting pro-
duced by the signal FF when both the input signal and the
first integrator output signal have the same sign.
0.03
[
t 0.02
0.025
0.015
0.01
0.005
n
-1.5
-1
-0.5
0
0.5
1
Integrator Output Voltage (+l V Reference Voltage) [VI
5
Figure 3. Simulated histograms of the first integrator out-
put voltages for conventional and proposed L?,
modulators
The power spectral densities of the output bitstreams ob-
tained from the conventional and the proposed modulator
with the same input signal are shown in Fig. 4. The two
curves are identical, thus confirming that no performance
degradation occurs due to the changes in the architecture.
The advantages of the proposed XA modulator architecture
become evident when we introduce a saturation at 'Vrc, of
the first integrator output. The power spectral densities ob-
tained in this case from the conventional and the proposed
modulator are reported in Fig. 5. The conventional modula-
tor shows a strong degradation of noise floor and harmonic
distortion, while the performance of the proposed modula-
tor remain ideal.
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1 o4
1 o2
10" 1 oo
Normalized Frequency
Figure 4. Simulated power spectral density of the output
bitstream for conventional and proposed XA modulators
under ideal conditions
0
-20
L i . i 4
gal
5 n
%-so
H
m
R
'ci -100
-120
-140
-160
1 o4
10"
10-l
1 oo
Normalized Frequency
Figure 5. Simulated power spectral density of the output
bitstream for conventional and proposed XA modulators
with limited integrator output swing (k V,,f)
3. CIRCUIT IMPLEMENTATION
The proposed technique has been verified on second-order
XA modulator implemented using the switched-capacitor
(SC) technique. The schematic diagram of the modulator is
shown in Fig. 6 [3]. The circuit consists of two SC integra-
tors ( CIl and CI, are the two pairs of integrating capacitors),
three latched comparator and a digital section.
The output of the two auxiliary comparators (Qo and Q;J
as well as the output bitstream of the modulator with and
without half clock period delay (Q, and Q2) are delivered to
the digital section which implements the required functions
(additions and integration) and generate suitable clock
phases (QF, @GI. @Gz. QG3) for the feedforward and feed-
@l
Figure 6. Schematic diagram of the SC implementation
of the proposed second-order I A modulator
back paths.
The SC branches CRI, C,,, C2? and C23 with the clock phas-
es and capacitance values used implement all of the re-
quired feedforward and feedback coefficients with the
proper sign and weight.
The operational amplifier used is based on a fully differen-
tial, folded cascode transconductance stage with SC com-
mon mode feedback, while the latched comparator consists
of a differential stage followed by a double regenerative
loop [4].
4. EXPERIMENTAL RESULTS
A prototype of the XA modulator has been fabricated in a
double-poly double-metal 0.8 pm CMOS process in order
to demonstrate the proposed architecture. Fig. 7 shows a
micrograph of the chip. The area of the device. including
pads, is 2.35 mm x 1.75 mm. The chip consumes 330 FA
from a 3.3 V power supply. The clock frequency of the
modulator is 1 MHz.
The measured histogram of the first integrator output volt-
age, shown in Fig. 8, confirms that with the proposed archi-
tecture the voltage swing needed for the correct operation of
the modulator is limited to 0.5 times the reference voltage.
Fig. 9 and Fig. 10 show the measured power spectral densi-
ty of the output bitstream and the measured SNR as a func-
tion of the input signal amplitude obtained with an
oversampling ratio of 5 12, respectively. The noise floor due
to the kTIC noise of the input branches together with the ex-
pected second-order noise shaping lead to a peak SNR of
78 dB, corresponding to 12.6 bits of resolution.
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I AI
70
60-
50
Figure 7. Chip micrograph of the proposed second-order
XA modulator
,”
\
-
/
-
/’
0.035
0.03
0.025
p 0.02
2
0.015
-
Q
0 . 0 1
0.005
Integrator Output Voltage (51 V Reference VoMage) [VI
Figure 8. Measured histogram of the first integrator out-
put voltage for the proposed XA modulators
-20
-
5 i
2 -40
-
U)
5
g
-
U
a
0
( r
v)
5 -80
a0
-100
-120
1 od
10
l o 2
10’ 1 oo
Normalized Frequency
Figure 9. Measured power spectral density of the output
bitstream for the proposed XA modulator
01
-80
-70
-60
-50
Signal Amplitude [dB]
-40
-30
-20 -10
0
Figure 10. Measured SNR as a function of the input sig-
nal amplitude for the proposed XA modulator with an over-
sampling ratio of 5 12
5. CONCLUSIONS
This paper presented a novel EA modulator architecture
which limits the output swing of the first integrator to 0 . 5
times the reference voltage without degrading the perfor-
mance, thus allowing us to use an input dynamic range a:;
wide as the entire supply voltage. This result is achieved by
replacing the feedback path from the output to the input o ; F
modulator with a local feedback around the first integrator
and restoring the global feedback information at the output
of the first integrator. The additional circuitry required in
the proposed architecture is limited to two comparators, a
digital integrator and a low-resolution DAC. To validate the
proposed technique we implemented a SC second-order Xih
modulator, but this approach can be used also for higher or-
der loops. The measurements on the fabricated prototype
confirm the expected reduction of the first integrator output
swing with no degradation of the overall modulator perfor-
mances.
REFERENCES
[I] P. Malcovati, F. Maloberti and M. Terzani, “An High-Swing,
1.8 V, Push-pull OPAMP for Sigma-Delta Modulators”,
Proc. ICECS ‘9S, Lisbon, Portugal, pp. 33-36, 1998.
[2] B. E. Boser, B. A. Wooley, “The Design of Sigma-Delta
Modulation Analog-to-Digital Converters”, IEEE J. o f Solid-
Stare Circ., vol. 23, pp. 1298-1308, Dec. 1988.
[3] P. Malcovati, A. Haberli, F. Mayer, 0. Paul, F. Maloberti and
H. Baltes, “Combined Air Humidity and Flow CMOS
Microsensor with On-Chip 15 Bit Sigma-Delta AK)
Interface”, Pi-oc. VLSI ‘95, Kyoto, Japan, pp. 45-46, 1995.
[4] P. Malcovati and F. Maloberti, “An Integrated Microsystem
for 3D Magnetic Field Measurements”, IEEE Trans. 011 I ~ u r t :
alld Meas., 49, pp. 341-345,2000.
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