Conference Paper

High performance 0.18 μm SOI CMOS technology

IBM Semicond. Res. & Dev. Center, Hopewell Junction, NY
DOI: 10.1109/IEDM.1999.824243 Conference: Electron Devices Meeting, 1999. IEDM Technical Digest. International
Source: IEEE Xplore

ABSTRACT A 0.18 μm SOI CMOS technology is presented. Key features in
this technology are: more aggressive gate lithography (equivalent to
0.15 μm half pitch generation) and devices than previously reported
0.18 μm CMOS technology, low dose SIMOX SOI substrate, dual gate
oxide, low ε BEOL insulator, and 7 layer copper metalization.
Inverter delay of less than 6.5 ps has been achieved with this
technology. A POWER4TM test chip was built using the 0.18
μm SOI technology and has demonstrated performance above 1 GHz