Conference Paper

Performance Comparison of Chip-Level Equalizers in the HSDPA System

Dept. of EECS, Korea Adv. Inst. of Sci. & Technol., Daejeon
DOI: 10.1109/ANSS.2007.32 Conference: Simulation Symposium, 2007. ANSS '07. 40th Annual
Source: IEEE Xplore

ABSTRACT High speed downlink packet access (HSDPA) is devised to enable the current 3G system to accommodate more data throughput for mobile users. The three main features of the HSDPA system are the adaptive modulation and coding (AMC), the hybrid automatic repeat request (HARQ) and the fast scheduling. It would be possible to obtain the downlink speed of up to 14Mbps in HSDPA using these three features. However, the standard describes only about the specification of the Node-B, various kinds of receivers, which may have different internal structures, can be implemented. In general, the common receiver means a rake receiver. Because the equalizer can reduce the multiple access interference (MAI) unlike the rake receiver, it can be an alternative to the rake receiver, especially in the HSDPA system. In this paper, we compare the performance of several equalizers for HSDPA. The simulation results provide the useful information to the receiver designers that which kind of equalizer is appropriate for their design in view of trade-off between performance and complexity

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