Conference Paper

A 20 GS/sec analog-to-digital sigma-delta modulator in SiGe HBT technology

Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA
DOI: 10.1109/CICC.2006.320909 Conference: Custom Integrated Circuits Conference, 2006. CICC '06. IEEE
Source: IEEE Xplore


This paper presents a monolithic continuous-time 2nd-order analog-to-digital sigma-delta modulator implemented in third-generation, 200 GHz SiGe HBT technology. The modulator can operate at a sampling rate of 20 GS/sec with SNRs of 30.5 dB over a signal band from DC to 312.5 MHz, and 51 dB over 1 MHz bandwidth. Operating off a +3.5 V power supply, the modulator dissipates a total of 490 mW. The die occupies an area of 1.58 times 1.7 mm2

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    • "PERFORMANCE SUMMARY OF 16 ADC of the power (0.74 W) is consumed by the clock path and output driver with the rest being dissipated by the filter, DACs, and quantizer. In comparison to recently-published ADCs (Fig. 24), this ADC achieves the best figure of merit (FoM) [20] FoM (19) among the bandpass designs [6]–[9], [22] and comparable performance to the low-pass ADCs of [18] and [23], which were implemented in 200-GHz InP and SiGe HBT technologies, respectively. Although the output stream of the ADC must be decimated to lower rates, a low-power 40-Gb/s decimation filter consisting of a DEMUX and digital filters can be realized in SiGe BiCMOS with only 10 mW per latch [21] at 2.5 V. "
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    ABSTRACT: This paper presents a 40-GS/s continuous-time bandpass DeltaSigma analog-to-digital converter centered at 2 GHz for wireless base station applications. The ADC consists of a fourth-order loop with multiple feedback and is designed entirely in the s-domain. The circuit achieves an SNDR of 55 dB and 52 dB over bandwidths of 60 MHz and 120 MHz, respectively, and an SFDR of 61dB with a single-ended IIP3 of +4 dBm. The center frequency is tunable from 1.8 to 2 GHz. It employs a G<sub>m</sub>-LC<sub>VAR</sub> filter based on a MOS-HBT cascode transconductor with an NFMIN of 2.29 dB. The entire circuit is implemented in a 130-nm SiGe BiCMOS technology with 150-GHz f<sub>T</sub> SiGe HBT and dissipates 1.6 W from a 2.5-V supply
    IEEE Journal of Solid-State Circuits 06/2007; 42(5-42):1065 - 1075. DOI:10.1109/JSSC.2007.894794 · 3.01 Impact Factor
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    ABSTRACT: A low-pass continuous-time delta-sigma data converter with adjustable sampling rate from 20-50 GS/s has been demonstrated in a production 165 GHz-f<sub>T</sub> 130-nm SiGe BiCMOS process. The ADC exploits the high transistor f<sub>T</sub> of modern silicon technologies to achieve an ENOB of 7 bits over a 500 MHz passband and 6 bits over a 1 GHz passband while consuming 350 mW from a 2.5 V supply (650 mW including on chip clock distribution and output driver); marking the first delta-sigma ADC to reach a bandwidth of 1 GHz. At the system-level, the analysis of a detailed behavioral model brought to light the high dependency of modulator performance on metastability. An analytical expression linking quantizer gain and number of bits to performance was therefore derived and used to estimate the theoretical limitations imposed by metastability.
    IEEE Journal of Solid-State Circuits 06/2009; 44(5-44):1401 - 1414. DOI:10.1109/JSSC.2009.2015852 · 3.01 Impact Factor