A programmable operational amplifier (OpAmp) concerning noise and power consumption is described. Key design issues for achieving programmability of a preselected OpAmp architecture are discussed. Experimental results for a 0.35 mum CMOS OpAmp show either ultra low noise of 2 nV/radicHz or low power consumption of 140 muW. The OpAmp remains stable over the whole range of programmability
[Show abstract][Hide abstract] ABSTRACT: The design and realization of an ultra-low noise operational amplifier is presented. Its applications are integrated low-frequency noise measurements in electronic devices and on- chip phase-noise measurement circuit. This paper discusses the SiGe:C BiCMOS 0.25 mum design improvements used for low noise applications. The proposed three-stage operational amplifier uses parallel bipolar transistor connection as input differential pair for low noise behavior. This operational amplifier provides both low noise and high gain performances. This operational amplifier has an area of only 660 times 250 mum<sup>2</sup> with an equivalent input noise floor of only 1.1 nV/ radicHz square root at 10 kHz. The measured noise characteristics (versus total power consumption) are better than those of most operational amplifiers commonly adopted in low-frequency noise measurements. The AC gain is 83 dB and the unity gain bandwidth is 210 MHz, with a total current consumption of 18 mA at 2.5 V supply voltage.
"The OpAmp has been realised as a proof of concept in a 0.35 µm CMOS technology. For keeping things simple, we chose this time to omit the chopper modulation, which was contained in the original circuit for elimination of 1/f-noise . "
[Show abstract][Hide abstract] ABSTRACT: The problem of variable phase margin of our programmable operational amplifier (OpAmp), which was presented at ESSCIRC 2006, has been solved. The OpAmp is programmable concerning noise and power consumption, while the phase margin is kept at an approximately constant value of 68deg for the whole range of programmability. Experimental results for a 0.35 mum CMOS OpAmp show either low noise of 3.6 nV/radicHz or low power consumption of 59 muW, and a phase margin variation of only Deltaphi<sub>res</sub> = 6deg.
33rd European Solid State Circuits Conference, 2007. ESSCIRC; 10/2007
"The proposed novel architecture is shown in Fig. 4. It consists of three identical operational amplifiers ,  and differs from commonly used instrumentation amplifier concepts in subtracting the DC-offset using the input V DC . The idea of this architecture is to subtract the DC-offset of the electrodes from the input signal V EL . "
[Show abstract][Hide abstract] ABSTRACT: A system-on-chip (SoC) approach for biomedical signal data acquisition in 0.35 µm 3.3 V CMOS technology is presented. The SoC is adaptable for multiple specific applications and is intended to be utilized in a low-power or a low-noise biomedical domain. A new approach for CMRR calibration technique has been used achieving a CMRR value larger than 80 dB at large DC-offsets.
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