Conference Paper

High performance spiral inductors embedded on organic substrates for SOP applications

Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA
DOI: 10.1109/MWSYM.2002.1012316 Conference: Microwave Symposium Digest, 2002 IEEE MTT-S International, Volume: 3
Source: IEEE Xplore


This paper presents the design, measured data, and systematic
analysis of spiral embedded inductors fabricated on standard organic
substrates using low-cost, large-area MCM-L technology. Several
configurations for inductors were investigated to optimize the inductor
layout dimensions such as conductor width, number of turns, inner
diameter, spacing between inductor and ground, and inductor area. A
maximum Q of 100 was measured for a 3.6 nH inductor at 1.8 GHz on an
organic substrate with a self resonance frequency of 10.6 GHz within an
inductor core area of 0.72 mm2. The effects of
configurational variables on inductor characteristics such as quality
factor, self-resonance frequency, and inductance are discussed. High-Q
inductors embedded on organic substrates can find numerous RF and
microwave system-on-package (SOP) applications, such as VCOs, IF/RF
bandpass filters, LNAs, etc., in which IC chips are flip-chip mounted on
the package substrate

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    ABSTRACT: One of the chief components in a RF/microwave circuit is the inductor. The performance of the inductor affects the performance of widely used circuits such as the voltage controlled oscillator (VCO), low noise amplifier, and filter in the RF front end. It is very important to design inductors for accurate values of inductances and sufficiently high quality factors for these microwave applications. A key challenge in achieving high unloaded Q for an inductor in a thin substrate is the ground separation. This thesis aims at addressing this issue and achieving high unloaded Q's in the range 150 - 200 for a ground separation of about 100 - 140 microns in the frequency range of 1 - 15 GHz. One port and inductors will be designed using Electromagnetic field solvers. Various topologies will be explored for 2D and 3D inductors with the aim of achieving the desired inductance density and Q parameters in a minimum area possible. In order to address the issue of ground separation, design modifications will include the use of patterned grounds to take advantage of the reduced parasitic capacitive coupling which enables a high Q factor. The objective of the thesis also includes demonstration of the usefulness of these high quality inductors in RF front ends. To this effect, proof of concept designs of LC band pass filters will be presented. To enable this design, capacitors will also be designed. An extensive library of the designed inductors will be presented as a part of the thesis. The designed components will be fabricated at the Packaging Research Center (PRC), Georgia Tech using organic substrate compatible processes. High frequency measurements will be made with the Vector Network Analyzer (VNA) along with suitable de - embedding to demonstrate the correlation between designed and fabricated results. Following this, circuit models will be built for the characterized inductors. M.S. Committee Chair: Prof. Rao Tummala; Committee Member: Prof. G.K. Chang; Committee Member: Prof. Maysam Ghovanloo
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    ABSTRACT: As the complexity of interconnects and packages increases and the rise and fall time of the signal decreases, the electromagnetic effects of distributed passive devices are becoming an important factor in determining the performance of gigahertz systems. The electromagnetic behavior extracted using an electromagnetic simulation or from measurements is available as frequency dependent data. This information can be represented as a black box called a macromodel, which captures the behavior of the passive structure at the input/output ports. In this dissertation, the macromodels have been categorized as scalable, passive and broadband macromodels. The scalable macromodels for building design libraries of passive devices have been constructed using multidimensional rational functions, orthogonal polynomials and selective sampling. The passive macromodels for time-domain simulation have been constructed using filter theory and multiport passivity formulae. The broadband macromodels for high-speed simulation have been constructed using band division, selector, subband reordering, subband dilation and pole replacement. An automated construction method has been developed. The construction time of the multiport macromodel has been reduced. A method for reducing the order of the macromodel has been developed. The efficiency of the methods was demonstrated through embedded passive devices, known transfer functions and distributed interconnect networks. Ph.D. Committee Chair: Dr. Madhavan Swaminathan; Committee Member: Dr. Abhijit Chatterjee; Committee Member: Dr. Andrew F. Peterson; Committee Member: Dr. C. P. Wong; Committee Member: Dr. Sung Kyu Lim
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    ABSTRACT: In today's semiconductor-based computer and communication technology, system performance is determined primarily by two factors, namely on-chip and off-chip operating frequency. In this dissertation, time-domain measurement-based methods that enable gigabit data transmission in both the IC and package have been proposed using Time-Domain Reflectometry (TDR) equipment. For the evaluation of the time-domain measurement-based method, a wafer level package test vehicle was designed, fabricated and characterized using the proposed measurement-based methods. Electrical issues associated with gigabit data transmission using the wafer-level package test vehicle were investigated. The test vehicle consisted of two board transmission lines, one silicon transmission line, and solder bumps with 50um diameter and 100um pitch. In this dissertation, 1) the frequency-dependent characteristic impedance and propagation constant of the transmission lines were extracted from TDR measurements. 2) Non-physical RLGC models for transmission lines were developed from the transient behavior for the simulation of the extracted characteristic impedance and propagation constant. 3) the solder bumps with 50um diameter and 100um pitch were analytically modeled. Then, the effect of the assembled wafer-level package, silicon substrate and board material, and material interfaces on gigabit data transmission were discussed using the wafer-level package test vehicle. Finally, design recommendations for the wafer-level package on integrated board were proposed for gigabit data transmission in both the IC and package. Tummala, Rao R., Committee Member ; Swaminathan, Madhavan, Committee Chair ; Wong, C.P., Committee Member ; Peterson, Andrew F., Committee Member ; Kenney, J. Stevenson, Committee Member. Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2005. Directed by Madhaven Swaminathan. Includes bibliographical references.
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