Article

Systolic product–sum circuit for GF((22)m) using neuron MOSFETs

{ "0" : "Electrical and Computer Engineering Department, Wayne State University, Detroit, MI 48202, USA" , "2" : "Composite and binary galois fields" , "3" : "MVL" , "4" : "Quaternary logic" , "5" : "Neuron MOSFET"}
Integration, the VLSI Journal DOI:10.1016/j.vlsi.2004.12.001 pp.29-47

ABSTRACT A quaternary systolic product-sum computation circuit for GF((22)m) using voltage-mode vMOSFETs is presented. The design is composed of four basic cells connected in a pipelined fashion. Each basic cell is composed of 2 Galois field adders, 2 Galois field multipliers, and 7 flip-flops. The circuit was simulated using Affirma Analog Circuit Design Environment tool supplied by Cadence, and it has shown to perform correctly. The quaternary circuit for GF((22)2) shows a significant amount of savings in both transistor count and number of connections compared to the one that uses the binary field GF(24).

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Keywords

2 Galois field adders
 
2 Galois field multipliers
 
7 flip-flops
 
Affirma Analog Circuit Design Environment tool
 
binary field GF(24)
 
pipelined fashion
 
quaternary systolic product-sum computation circuit
 
voltage-mode vMOSFETs