Silicon bipolar transistor: a viable candidate for high speed applications at liquid nitrogen temperature
ABSTRACT Despite its inherent speed advantage over CMOS technologies under loaded conditions, the silicon bipolar transistor historically has been dismissed as a viable candidate for digital applications in the 77 K environment. The principal reason for this is the well documented degradation in the device current gain at low temperatures. It is demonstrated in this paper that this conclusion is no longer valid with respect to state-of-the-art devices. The transistors used in this investigation have sufficient current gain at 77 K for most digital applications without intentional profile modification. Emitter coupled logic (ECL) circuits switch at < 100 ps speeds at 77 K, and reduced logic-swing operation offers the benefits of an attractive power-delay product. This paper examines the physics, design and performance issues associated with the low temperature operation of silicon bipolar transistors, and discusses the potential advantages of such devices for high speed applications in future low temperature computer systems.
- SourceAvailable from: Gustaaf Borghs[Show abstract] [Hide abstract]
ABSTRACT: A model for bandtailing is built into the 1-D device simulator SEDAN. The influence of bandtails on the current gain of a state-of-the-art bipolar transistor is examined. It is shown that for transistors with high emitter doping, bandtail effects decrease the current gain significantly. This reduction in current gain is more pronounced at low temperature.Solid-State Electronics 05/1992; 35(5):699-704. DOI:10.1016/0038-1101(92)90040-J · 1.51 Impact Factor
- [Show abstract] [Hide abstract]
ABSTRACT: Below approximately 40 K, conventional CMOS technologies show radical departures from room temperature behavior and classical theory, confounding attempts to design readout circuits that have desirable and predictable behavior. Though the effects often seem difficult to explain, they are in all cases due to the effects of carrier freezeout. We have extensively investigated the device properties of CMOS FETs at temperatures very close to absolute zero and conducted a series of process optimizations designed to overcome anomalies that dominate the device behavior. The resulting technology has been used to build readouts for very long wavelength extrinsic silicon detectors, including staring arrays of significant complexity (256 x 256 pixels). Large die sizes (450 mils) have been produced with high yields (in excess of 50 percent) using this process.Proceedings of SPIE - The International Society for Optical Engineering 06/1992; 1684:2-39. DOI:10.1117/12.60492 · 0.20 Impact Factor
- [Show abstract] [Hide abstract]
ABSTRACT: The DC design considerations associated with optimizing epitaxial Si- and SiGe-base bipolar transistors for the 77-K environment are examined in detail. Transistors and circuits were fabricated using four different vertical profiles, three with a graded-bandgap SiGe base, and one with a Si base for comparison. All four epitaxial-base profiles yield transistors with DC properties suitable for high-speed logic applications in the 77-K environment. The differences between the low-temperature DC characteristics of Si and SiGe transistors are highlighted both theoretically and experimentally. A performance tradeoff associated with the use of an intrinsic spacer layer to reduce parasitic leakage at low temperatures and the consequent base resistance degradation due to enhanced carrier freeze-out is identified. Evidence that a collector-base heterojunction barrier effect severely degrades the current drive and transconductance of SiGe-base transistors operating at low temperatures is providedIEEE Transactions on Electron Devices 04/1993; DOI:10.1109/16.199358 · 2.36 Impact Factor