OpenFPGA CoreLib core library interoperability effort

Department of Computer Science & Engineering, University of California Riverside, Riverside, CA 92521, USA
Parallel Computing (Impact Factor: 1.51). 05/2008; 34(4-5):231-244. DOI: 10.1016/j.parco.2008.03.004
Source: DBLP


This paper begins by summarizing the goals of the OpenFPGA CoreLib Working Group to facilitate the interoperability of FPGA circuit cores within a variety of FPGA design tools, including high-level programming tools targeting FPGA architectures. This effort is contrasted with other IP reuse efforts. The paper reviews the current approach used by several high-level language compilers to integrate IP within their tool. The CoreLib approach for standardizing this IP integration is proposed followed by an example that demonstrates its utility. Finally, the current state of the effort and future plans are presented.


Available from: Walild A. Najjar
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    • "In Section IV, we propose solutions to these problems. The OpenFPGA CoreLib [9] working group focused on examining the IP-XACT Schema and proposed extensions for facilitating core reuse into HLLs. Wirthlin et al. [10] used XML to describe common IP block elements and defined their own schema using IP-XACT syntax. "
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    • "However, the main barrier is that designing sophisticated FPGA-based systems is a complex engineering challenge. In general, more modular design and reuse is required, along with higher levels of abstraction in design specification [1]. "
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    • "In terms of recent research in this area, the ShapeUp work has closest relationships with the CHREC XML work of Wirthlin et al. [9] [10]. This features an XML data schema that goes beyond current IP-XACT to address module metadata requirements for reconfigurable computing. "
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