Methodology for Design, Measurements and Characterization of Optical Devices on Integrated Circuits

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Methodology for Design, Measurements and
Characterization of Optical Devices on
Integrated Circuits
G. Castillo-Cabrera1,3, J. García-Lamont2 and M. A. Reyes-Barranca3
1Superior School of Computing (ESCOM), National Polytechnic Institute (IPN),
2Institute of Basic Science and Engineering, CITIS, Hidalgo State University,
3Electrical Engineering Department, SEES, CINVESTAV-IPN,
Mexico
1. Introduction
The main application of optical devices is image processing which is a research field still in
study for a wide variety of applications, such as video digital cameras for entertainment use,
pattern recognition based in artificial neural networks, real time object tracking, clinical uses
for repair by stimulation parts of visual system and artificial vision for application in silicon
retinas, among others. So, it is important to evaluate the performance of available integrated
photo-sensor devices used in these applications, considering issues as noise, resolution,
processing time, colour, etc. Actually, there are several technologies available for integration
of photo devices, commonly CCD, BiCMOS and GaAs. Although all of them are usually
applied in image acquisition systems, there are still some performance aspects that should
be optimised, as voltage levels, leakage currents, high fabrication costs, etc., so research is
still being done to overcome these limitations. Standard CMOS integrated circuit technology
is also an attractive alternative, since devices like phototransistors and photodiodes can be
implemented as well. The foremost advantage of CMOS devices is its availability in
standard technology. It should be mentioned that this technology has also some limitations
but since fabrication of CMOS integrated circuits has low costs, exploration of the potential
of new technologies for image processing is still an interesting field. Besides, algorithms can
be implemented along for tasks such as border detection (space vision), movement detection
(space-time vision), image enhancement (image processing vision) and pattern classification
or recognition (neuro-fuzzy vision).
Considering the state of the art (Aw & Wooley 1996; Storm & Henderson, 2006; Theuwissen,
2008), as well as clinic approaches (Zaghloul, & Boahen, 2004), in this work, a chip was
designed and fabricated, with two possible photo-sensor structures: p+/N-well/p-substrate,
for phototransistors and N-well/p-substrate, for photodiodes, through the standard 1.5µm
AMI’s- , N-Well technology. In the future, it is the intention to design a second chip that
must include electronics for image processing with pulse frequency modulation (PFM), once
the characterization gives enough information about the performance of the stages studied.
A complete description is given.

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2. Devices Involved, type of structures
After the CCDs, the new generations of optical devices are based in standard CMOS
technology. Experimental study based is here presented, about two typical structures in the
field of art, namely, phototransistor and photodiodes which were designed and fabricated
through the standard 1.5µm AMI’s- technology. Technically those are known as “structures
P+/N-Well/P-substrate” and “structures N-Well/P-substrate” respectively, which are
presented by Fig. 1.


(a) (b)
Fig. 1. Optical devices, (a): P+/N-Well/P-substrate, (b): N-Well/P-substrate
In the former, Fig. 1(a), P+/N-Well/P-substrate, the P+/N-Well is being an active junction
as well as N-Well/P-substrate junction. An active junction is one in which two
semiconductors with different conductivity, “p” and “n” type, are joined and electrically
interacting. N-Well is a diffused region n-type on substrate. P+ on N-Well is an implanted
material and also serves as low resistive ohmic contact. N+ on N-Well is an n-type
implanted region and solely is used as low resistive ohmic contact. P+ on P-substrate is an
implanted p+-type material and is used as low resistive ohmic contact. Terminals E, B and C
are Emitter, Base and collector respectively in the phototransistor.
In the last one, Fig. 1(b), N-Well/P-substrate, there is only one active junction. N+ and P+
are implanted regions which does low resistive ohmic contact with N-Well and P-substrate
respectively.
Both, structures P+/N-Well/P-substrate and N-Well/P-substrate, symbols are presented by
the Fig. 2.


(a) (b)
Fig. 2. Symbols for optical structures (a): P+/N-Well/P-substrate, (b): N-Well/P-substrate
3. Circuital architecture of pixel for characterization
3.1 Components of architecture
Fig. 3 presents the pixel architecture which has resulted efficient for optical devices
characterization. It consists in optical device, four transistors, a source of current and buffer

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for readout. The common source amplifier consists, in M1 transistor and current source Isc,
and it is used to handle the photocurrent. M2 is row select transistor and is not part of
amplifier strictly speaking, however its position play an important role on this architecture,
as will be shown in section 4. Photocurrent, from optical device, is integrated at the parasitic
capacitance of the p-channel transistor M1, between node 2 and substrate, which is tied to
ground. Assuming that photocurrent is constant, the relation of integrated voltage can be
obtained by using the relation qC V
=⋅
in the parasitic capacitance.

t
1
C
int
0
Vidt
Δ
=∫
(1)
where

dq
dt
i =
(2)
MSHUT along with signal VSHU controls the exposition time Δt. MREST along with signal
VRES have as function to reset the nodes 1 and 2 at level Vreset. Optical devices can be
P+/N-Well/P-substrate or N-Well/P-substrate structures. BUFFER OUTPUT provides
power to avoid disturbance during readout.


(a) (b)
Fig. 3. (a) Architecture of pixel, (b) Optical device
Transistors MSHUT and MREST operate as switches in order to integrate the photocurrent
generated in the photo-sensor at a given time and operation frequency. Fig. 4 shows the
waveforms of their respective gate voltages. Integration time Δt, takes place while MSHU is
on and MRES is off. During this time, the photocurrent is converted to voltage at the gate of
transistor M1 (node-2 in Fig. 1). The relation between the integrated voltage and
photocurrent is expressed in Eq. (1), assuming that the photocurrent is uniform in time. The
DC voltage source, Vreset, is the reference voltage from which integration of the
photocurrent is carried out.

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3.2 Signals of control


Fig. 4. Waveform of signals shutter and reset

()
/
int
ICVT
phT
=ΔΔ
(3)
where:
I
:
ph
photocurrent from the photo-device.
T
C :
ΔV
T
Δ
Av:
In addition, Vreset sets the quiescent point of the amplifier. Fig. 4 shows the input voltage
pulses applied to the gate of MRES and MSHUT, respectively.
Since the objective of this work is to propose a methodology for the characterization of
photo-devices and pixel architectures, the design was made considering those parameters
affecting the performance of pixels and the way they will be measured. The design was
carried out with the more simple architecture. Unlike what was reported with current
amplifiers in the current-mode readout configuration (Philipp et al 2007), the amplifier is
configured for voltage-mode operation in this work. From results obtained with this design,
useful information can be processed and analysed considering a specific application,
regarding factors such as the spectral response and silicon integration area of p+/N-well/p-
substrate phototransistors and N-well/p-substrate photodiodes, as well as integration time,
integrated voltage, transistors’ aspect ratio and reference voltage used, for instance.
Considerations about technology parameters, is important also in the definition of the
dependence of the response and the architecture operation upon the photo-device structure.
Here, we present the electronic design, layout, simulations and some measurements on the
fabricated chip. This prototype was made using the 1.5µm AMI’s technology. The chip
contains five pairs of phototransistors and five pairs of photodiodes, with one instance of
each pair covered with metal for dark current characterization purposes. Results reported
capacitance at node-2
integrated voltage in
integration time
amplifier’s gain
int
:
T
C (
int
/
measured
V
= Δ
VAv
Δ
)
:

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here are only from those devices having an area of (9µm)x(9µm). Bigger photo-devices were
also measured, but as they saturated the amplifier, no useful results were obtained. A
drawing is given in the Fig. 5 which is showing the fabricated array.


Fig. 5. Drawing for the array of optical devices
4. Circuit analysis
Now, doing reference to the Fig. 3, some design criteria for the circuit are defined. (1)
Transistors MREST and MSHUT are used as switches, so their sizes can be drawn with
minimum dimension features allowed by the technology. (2) Channel modulation effects
must be avoided with M1, therefore its channel length should be at least five times the
minimum dimension allowed. (3) For proper operation of the amplifier, it is recommended
to choose a stable current source for biasing, thus, a cascode configuration was selected and
designed for sourcing 20µA. (4) By adjusting the current source and Vreset the voltage gain
of the amplifier it is varied, giving a useful degree of freedom for the characterization of the
architecture and different devices, including the possibility another kind of not optical
integrated sensors. (5) Transistor M2 it is inserted into the amplifier since it is a standard
way for selecting row within an array. However, the role of M2 on the amplifier here
proposed must be analyzed. (6) Finally, a standard buffer circuit is used for provide of
power to the output.
Fig. 6 (a) shows the schematic of the cascode current source used for biasing the amplifier.
Transistors involved in the amplifier are M1, M2, M4 and M6. Fig. 6 (b) shows the
equivalent circuit for the amplifier and the cascode current source, used to find a
mathematical relationship between the voltage gain and the size of M2.
From Figure 4(b),
identifiers for transistors M1, M4 and M6, respectively. A circuit analysis gives the following
expression for the output voltage,
out
V
:
sr is the channel resistance of M2; here, subscripts 01, 04 and 06 are

01 1
r i
204 3
r i
06 2
r i
0
s
r i
+++=
(4)

2111
msg
iigv
−=
(5)