A Time-Delay Suppression Technique for Digital PWM Control Circuit

Abstract

This paper describes a digital PWM controller IC without A/D converters. The analog timing converter (ATC) is proposed for output voltage sensing. In this system, analog circuit are realized with an comparator and an D/A converter.

Full text

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A Time-Delay Suppression Technique for Digital PWM Control Circuit 389
X

A Time-Delay Suppression Technique
for Digital PWM Control Circuit

Yoichi Ishizuka
Nagasaki University
Japan

1. Introduction

Recently, power management has been introduced to improve the power efficiency of Micro
Processing Unit (MPUs), Field Programmable Gate Array (FPGAs) and Digital Signal
Processor (DSPs). The power management system includes a full operation mode, standby
mode, and sleep mode. The clock frequency, core voltage and/or core current are changed
in each mode accordingly. As a result, the output current of the point-of-load (POL) DC-DC
converters is intermittent and has a high slew rate. A low output voltage, a large output
current and a high speed response are required for the POL. In such a condition for the
control circuit, highly accurate and high-speed control demands that the tolerance of the
output voltage becomes internally severe, advanced by speed-up and lowering of the
voltage of the MPUs, FPGAs and DSPs. A general control method is pulse width
modulation (PWM) control with PID. Generally, such control circuits are composed with
analog circuits and/or simple combination digital circuits.
In these days, robustness or flexible controls for versatile conditions are demanded which
cannot accomplished with analog control circuit. For the control purpose, DPWM control is
a one of appropriate technique (Edward Lam, Robert Bell, and Donald Ashley (2003),
A.V.Peterchev and S.R.Sanders (2003), B.J.Patella, A.Prodic, A.Zirger and D.Maksimovic


SW1
SW1

Ei
Ei
CO
CO
eO
eO
SW2
SW2
iO
iO
RO
RO
iL
iL
Drive
CircuitCircuit
ADCADC ADC
Digaital
ControllerController
PWM PWM
Drive
Digaital

Fig. 1. Common digital control DC-DC converter.

(2004), D.Maksimovic, R.Zane, and R. Erickson (2004), S.Saggini, D.Trevisan and
P.Mattavelli (2007), S.Saggini, E.Orietti, P.Mattavelli，A.Pizzutelli and Bianco(2008)).
18

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Trends in Telecommunications Technologies390

Digital control or DPWM can accomplish robust and flexible power control with soft-tuned
parameters and will become popular control technique.
Although, there are some disadvantages in cost and speed, against analog control circuit.
Especially, A/D converter circuit, which doesn’t need for analog control, is the one of the
key circuits which effects on cost and speed. Generally, A/D converter is located in front of
digital controller as shown in Figure 1. Therefore, the transition speed of A/D converter
directly effects on the response speed of the control circuit. And, the cost and speed are
always trade off problem. This problem is especially serious in POL DC-DC converter which
is required to design the control circuit in relatively low-cost and high speed control
response. Moreover, generally, there is sample-hold circuit in front of A/D converter which
degrades the response speed.
A delay in any feedback system degrades the stability and damping of the system.
Especially, in DPWM, if a total of the delays described in above become larger than on-term
of one switching period, a factor of A/D converter becomes Vq/Z shown in Figure 2 where
Vq is a coefficient constant.
An objective of this paper is to design high speed and low cost voltage sensing circuit for
DPWM control circuit for DC-DC converter. And, also real-time PID control method is
proposed. In Sec. II, the details of proposed system are described. In Sec. III, the some
characteristics of the system are confirmed with experimental results. Finally, in Sec. IV, the
summary is described.

r(k)e(k)
u(k)
C(z)C(z)
DPWM
+
-
y1(k)
H(z)
y2(k)
Vq/Z
y1
d
G(s)G(s)

Fig. 2. Control System.

2. Proposed System

We propose a scheme of a digital control and DPWM circuit for DC-DC converter without
A/D converter shown in Figs.3 and 4, respectively. In this proposed control circuit, most
components are digital components. Analog components for the control circuit are
essentially only D/A converter and analog comparator. Theoretical waveforms of each part
are shown in Figure 5. The control circuit is composed of three major blocks.

2.1 Analog-Timing Converter (ATC)
The first block is ATC block which detects the output voltage eo and outputs the detected
signal to latch register. The maximum output value of D/A converter DAC is set as a sum of
the output reference voltage of DC-DC converter Vref and margin . A digital staircase
waveform data, pre-stored in memory Memory1, is output to DAC synchronized with a
system clock, and converted analog staircase waveforms Vref’ is compared with eo. As soon
as Vref’> eo, the comparator outputs high.

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A Time-Delay Suppression Technique for Digital PWM Control Circuit391

2.2 PID Control with Look-up Table

Ei
Ei
CO
CO
eO
eO
SW1
SW1
SW2
SW2
iO
iO
RO
RO
iL
iL
Drive
CircuitCircuit
DACDACDAC
Digital
ControllerController
Vref’
Vref’
Vcomp
Vcomp
PWM PWM
Drive
Digital

(a) Total Systems.

※ATC:Analog-Tim
Vg
ATC ATC
eo
Digital
ControllerController
Digital
DPWM
Latch
Resister

(b) Control blocks.
Fig. 3. Proposed DPWM Control DC-DC converter




















Fig. 4. Proposed digital control circuit.

address
88
DAC
V ref+
eo
Vref’
Vcomp
c(m )
10
Dff
y 2(k)
Q
8
Dff Q
9
Dff
nI (k -1)
Q
8
Dff
y 2(k -1)
Q
8
nI (k )
y 2 (k)
a
b
11
a -ba -b
u(k )
memory
11
memory
memory
22
memory
memory
33
memory
memory
44
memory
11
+1
PC
initial
address ’
System
CLK
Up
Counter
PLL
Up
Counter
Digital
Comparator
9
ATC
DPWM
Look -up Table
PWM
Digital
Controller
fS
f S’

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Trends in Telecommunications Technologies392


Fig. 5. Theoretical waveforms.

u(k) which is output from Memory2 is calculated by general PID digital control laws as

  
RefP
u ku K e kK n


where uRef is a reference value of u(k), e(k) is an digitalized error value between r which is
digitalized reference voltage Vref in switching term k, and nI(k)=nI(k-1)+e(k)( G. F. Franklin，
J. D. Powell and M. L. Workman (1997)). KP, KI and KD are a proportional gain, an integral
gain and an derivative gain, respectively.
Equation (1) can be transformed to

 
-
RefP
u kuK
K
A y k
A
 
k
 
e k -e k -1


IID
K

(1)

 
22
{ -1 --1 }
I
ID
I
Kr
K
nkyk
A


(2)

where
In Figure 4,
PID
A= K +K +K and y2(k) is digitalized output voltage eo in switching period k.


-1
I
I
K
A
K
A
ank

,


(3)



2
-1
D
byk

.
(4)

Memory3 and Memory4 store a and b, respectively.

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A Time-Delay Suppression Technique for Digital PWM Control Circuit393

In Eq. (2),
becomes the initial value of programmable counter PC of the term k. And, address’ which
indicates address of Memory2 is incremented with system clock and u(k) is called from
Memory2, simultaneously.


'=address
From (2) and (5),
 
-
RefP
u kuK

-a b in the term k is pre-calculated in the term k-1 and the obtained value
2
+ - y (k) a b.
(5)


{'}
I
KrA adress

.
(6)

Therefore, u(k) is determined as soon as y2 (k) is detected.

2.3 DPWM
In this system, on-term Ton(k) of DPWM signal is decided by u(k), which is normalized Ton(k),
and system clock frequency fS’as

Ton(k)=u(k)/fs’

u(k) is decided by latched value of Memory2.
In parallel with the processing of ATC block, the u(k) is called with system clock and latched
by ATC output as trigger.

3. Sensing Resolution

3.1 Resolution Increasing
As described in previous section, all blocks are synchronized with only one clock source.
From this advantage, all blocks are modified in easy way.
In this paper, voltage sense resolution increase of output voltage is proposed.
In proposed system, R-2R ladder type D/A converter is used. The output voltage is set
between Vref +(=Vref +) and Vref -. Therefore,

c(m)
='V
(7)

ref
-
ref
+
ref
n
ref
V+)V-(V
2

(2.8)

where n is bits. Also, least significant bit (LSB) voltage aLSB becomes

)V-(V
2
1
=a
-
ref
+
ref
n
LSB

(2.9)

In this paper, Vref- is set to Vref / 2. Almost n+1 bits resolution can be realized by n bits digital
system as shown in Table 1.

3.2 Sensing Time Delay
With this method, sensing time is increased. To avoid the time delay, the reference voltage
waveform data pre-set in memory1 Vref’ is modified as shown in Figure 6.