Efficient provably good OPC modeling and its applications to interconnect optimization.
ABSTRACT Optical Proximity Correction (OPC) is the most popular technique to handle design shape distortions arising from subwavelength lithography. Existing OPC models are typically very computationally expensive and thus not efficient to be incorporated for layout optimization. In this paper, we present an efficient, yet sufficiently accurate OPC cost model which can predict the optimal location of a wire segment for OPC optimization and give an upper bound of the interference amount, guaranteeing that the interference amount is never underestimated. Based on this cost model, we propose an OPC-aware wire perturbation algorithm for post-layout interconnect optimization. We show that the effects of wire perturbation have the concavity or monotonicity property which can dramatically reduce the search space for finding the optimal location of each wire for OPC optimization. Further, we can incrementally update the OPC cost of a wire by recomputing only the affected wires because of the property of superposition of our model. Experimental results show that our algorithm can efficiently obtain much better OPC results than a state-of-the-art OPC-friendly router, based on a leading commercial OPC tool.
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Conference Proceeding: Optical proximity correction (OPC): friendly maze routing.[show abstract] [hide abstract]
ABSTRACT: om with shorter wavelenahs is still too costlv and unstable. As the technology migrates into the deep submicron manufacturing (DSM) era: the critical dimension of the circuits is getting smaller than the lithographic wavelength. The unavoidable light diffraction phenomena in the sub-wavelength technologies have become one of the major factors in the yield rate. Optical proximity correction (OPC) is one of the methods adopted to compensate for the light diffraction effect as a post layout process. However, the process is time-consuming and the results are still limited by the original layout quality. In this paper, we propose a maze routing method that considers the optical effect in the routing algorithm. By utilizing the symmetrical property of the optical system, the light diffraction is efficiently calculated and stored in tables. The costs that guide the router to minimize the optical interferences are obtained from these look-up tables. The problem is first formulated as a constrained maze routing .problem, then it is shown to be a multiple constrained shortest path problem. Based on the Lagrangian relaxation method, an effective algorithm is designed to solve the problem.Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004; 01/2004
Conference Proceeding: Lithography-aware physical design[show abstract] [hide abstract]
ABSTRACT: Nanometer VLSI design is greatly challenged by the lithography limitations. Existing approaches in design for manufacturability (DFM) are mostly done post design, such as mask data preparation using various resolution enhancement techniques (RETs), rather than during design. To really bridge the gap between design and manufacturing, it is important to model and feed proper lithography metrics upstream to guide the proactive lithography aware physical design (LAPD). In this paper, we will discuss some key aspects of LAPDASIC, 2005. ASICON 2005. 6th International Conference On; 11/2005
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ABSTRACT: Due to the subwavelength lithography, manufacturing sub-90-nm feature sizes require intensive use of resolution-enhancement techniques, among which optical proximity correction (OPC) is the most popular technique in industry. Considering the OPC effects during routing can significantly alleviate the cost of postlayout OPC operations. In this paper, we present an efficient, accurate, and economical analytical formula for intensity computation and develop the first modeling of postlayout OPC based on a quasi-inverse lithography technique. The technique provides key insights into a new direction for postlayout OPC modeling during routing. Extensive simulations with SPLAT, the golden lithography simulator in academia and industry, show that our intensity formula has high fidelity. Incorporating the OPC costs computed by the quasi-inverse lithography technique for our postlayout OPC modeling into a router, the router can be guided to maximize the effects of the correction. Compared with a rule-based OPC method, the experimental results show that our approach can achieve 15% and 16% reductions in the maximum and average layout distortions, respectively.IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 02/2010; · 1.09 Impact Factor