A Cost-Efficient Bit-Serial Architecture for Sub-pixel Motion Estimation of H.264/AVC.
ABSTRACT This paper presents a new VLSI architecture for sub-pixel motion estimation in H.264/AVC encoder. It is based on an interpolation-free algorithm that causes a high level reduction on memory requirement, hardware resources and computational complexity. A high performance, bit-serial pipeline architecture is proposed for quarter-pixel accurate motion estimation which supports real-time H.264 encoding. Due to the bit-serial, modular and reusable architecture, it provides significant improvement in area cost (at least 39%) and increases the macroblock processing speed almost 6 times when compared with the previous designs. The proposed architecture is suitable for portable multimedia devices where the memory and power consumption are limited.
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ABSTRACT: This paper proposes fast sub-pixel motion estimation techniques having lower computational complexity. The proposed methods are based on mathematical models of the motion-compensated prediction errors in compressing moving pictures. Unlike conventional hierarchical motion estimation techniques, the proposed methods avoid sub-pixel interpolation and subsequent secondary search after the integer-precision motion estimation, resulting in reduced computational time. In order to decide the coefficients of the models, the motion-compensated prediction errors of the neighboring pixels around the integer-pixel motion vector are utilized. The prediction errors, here, were already obtained during the pixel accuracy motion search. Once the coefficients are determined, the models estimate motion compensated prediction errors at sub-pixel locations surrounding the integer-pixel motion vector, yielding the sub-pixel motion vector. The performance of the proposed methods, despite substantially lower computational complexity, is close to that of the conventional interpolation-and-search method.IEEE Transactions on Consumer Electronics 09/2004; · 1.09 Impact Factor
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ABSTRACT: This paper presents a fast algorithm and its VLSI architecture for H.264 fractional motion estimation. Motivated by the high correlation of cost between neighboring fractional pel position, the proposed algorithm efficiently explores the neighborhood position around the minimum one and thus skips other unlikely ones. Thus, the proposed search pattern and early termination under constant quantization parameter can reduce about 50% of computation complexity compared to that in reference software but only with 0.1-0.2 dB peak signal-to-noise ratio degradation and less than 2% of bit rate increase. The VLSI architecture of the proposed algorithm thus can save 40% of area cost due to only half of the processing elements and save 14% of searching time when compared with the previous designIEEE Transactions on Circuits and Systems for Video Technology 01/2007; 17(5):578-583. · 1.82 Impact Factor
Conference Proceeding: An algorithm and its architecture for half-pixel variable block size motion estimation[show abstract] [hide abstract]
ABSTRACT: This paper presents an accurate half-pixel variable block size motion estimation algorithm and its hardware architecture. The proposed algorithm does not require interpolation of the reference frame pixels and has near performance to the conventional interpolation-search methods. These simplifications cause high level reduction in computational time and gate count without the need for internal or external half-pixel accuracy search memory. A simple, low latency, high throughput and fully utilized pipelined architecture of proposed algorithm is implemented in VHDL. The proposed hardware architecture uses shift registers for multiplication and pipelining technique and can support half-pixel accuracy variable block size motion estimation for the real time HDTV format (1920 times 1280 resolution and 30 Frames/sec).Telecommunications and Malaysia International Conference on Communications, 2007. ICT-MICC 2007. IEEE International Conference on; 06/2007