Crosstalk in Deep Submicron DRAMs.
ABSTRACT This study examines the effect of crosstalk on the operations of DRAMs that are implemented in deep submicron technology, 0.18 µm. An extensive simulation revealed that the coupling between word lines and between bit lines alter the cell contents during reading and writing operations as well as retention of the different cells The effect is more likely when the poly instead of aluminum is used. Coupling between bit and word lines did not have such serious outcome.
Conference Paper: An Investigation into Crosstalk Noise in DRAM Structures.[Show abstract] [Hide abstract]
ABSTRACT: The 2001 ITRS roadmap predicts continued aggressive progress towards deep submicron linewidths for at least the next 15 years. In this article we describe the results of a simulation study into the effects of crosstalk among DRAM wordlines and bitlines for present and future technology nodes predicted by the roadmap. An analog simulator was used to solve the associated transmission line equations derived from Maxwell's equations in the time domain. Hence, we not only considered interconnect resistances and capacitances, but also inductances and realistic wave propagation effects. The circuit parameters of the simulation models were extracted from standard DRAM geometries implied by the roadmap data. Various bitline-bitline and wordline-wordline coupling scenarios were then studied in simulation. Our results suggest that down until the 22-nm node, single bitline twisting will continue to be effective against bitline-bitline coupling, but that wordline-wordline coupling effects will become more problematic.10th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2002), 10-12 July 2002, Isle of Bendor, France; 01/2002
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ABSTRACT: This paper presents an approach for measuring crosstalk interference in digital CMOS VLSI circuits. The crosstalk sensor has been implemented in 0.8 μm AMS (Austria Mikro Systeme) technology and its design is based on NOR and NAND RS latches. The interference is produced by an up (down) transition in an affecting line. The crosstalk sensor is designed to measure crosstalk interference amplitude produced by capacitive coupling between long metal lines. The sensor is programmable for measuring some ranges of crosstalk amplitude. The sensor design is based on the dynamic behavior of basic NOR and NAND gates depending on the MOS transistor sizesOn-Line Testing Workshop, 2000. Proceedings. 6th IEEE International; 02/2000
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ABSTRACT: This study analyzes the effects of crosstalk-induced faults due to parameter variation during the manufacture of DRAMs. The focus is on read operations, which are sensitive to crosstalk and to neighborhood data patterns. Analytical studies and numerical simulations have been used to investigate a class of crosstalk reading faults (CRF) that read operations are susceptible to. The results reveal that there exist worst case data patterns in each physical RAM block and cell arrangement. The worst case data pattern occurs when neighboring and victim bit-lines switch to opposite values at the same time. If the bit-line arrangement is known, the test for the CRFs is quite trivial. If there is no knowledge of the internal chip structure, a deterministic pattern cannot be assigned and therefore a generic test method is needed. In this paper, a test algorithm is proposed that exhausts every state of any 3 or 5 bit-lines of a RAM block.Journal of Electronic Testing 01/2006; 22:173-187. · 0.45 Impact Factor