Crosstalk in Deep Submicron DRAMs.
ABSTRACT This study examines the effect of crosstalk on the operations of DRAMs that are implemented in deep submicron technology, 0.18 µm. An extensive simulation revealed that the coupling between word lines and between bit lines alter the cell contents during reading and writing operations as well as retention of the different cells The effect is more likely when the poly instead of aluminum is used. Coupling between bit and word lines did not have such serious outcome.
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ABSTRACT: Emerging nonvolatile memories such as phase change memory (PCM) have the potential to replace internal memories in embedded devices. In this brief, we propose to use PCM as image buffer in application-specific multimedia systems. To improve the lifetime of PCM-based image buffer, we first eliminate redundant writes using data comparison. After redundant write elimination, PCM cells with respect to lower order bits of pixels are written more frequently than those corresponding to higher order. Based on this observation, we show that the lifetime can be further improved either by wear leveling using periodical data reversion to make write traffic even across PCM cells or by application-level error tolerance evaluation without leveling. Experimental results demonstrate that with the proposed techniques, the lifetime of PCM-based image buffer can be improved significantly.IEEE Transactions on Very Large Scale Integration (VLSI) Systems 06/2014; 22(6):1450-1455. DOI:10.1109/TVLSI.2013.2266668 · 1.14 Impact Factor
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ABSTRACT: As dynamic random access memories (DRAMs) are becoming denser with technology scaling, more complex fault behaviors emerge; examples are leakage, coupling effects, and cell neighborhoods interaction. The neighborhood pattern sensitive fault (NPSF) model is suitable to address such faulty behaviors and identify them during the characterization and/or test of new DRAM chips. However, NPSF test algorithms are extremely time-consuming and therefore not economically affordable. In this brief, we show how layout information can be used to refine and significantly simplify the NPSF model and reduce the test time complexity. As a case study, the folded DRAM array is considered. A realistic NPSF model, the $Delta$ -type neighborhood, is introduced together with a time efficient test algorithm which is more than two-times cheaper than traditional ones. Even when incorporating bit-line influence and word-line coupling effects, along with NPSFs, the test algorithm time complexity almost remains unaltered. Therefore, the proposed approach makes NPSF testing economically affordable, and hence, suitable for the characterization/test of dense DRAMs in the nanoera.IEEE Transactions on Very Large Scale Integration (VLSI) Systems 06/2014; 22(6):1446-1450. DOI:10.1109/TVLSI.2013.2266281 · 1.14 Impact Factor
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ABSTRACT: This study analyzes the effects of crosstalk-induced faults due to parameter variation during the manufacture of DRAMs. The focus is on read operations, which are sensitive to crosstalk and to neighborhood data patterns. Analytical studies and numerical simulations have been used to investigate a class of crosstalk reading faults (CRF) that read operations are susceptible to. The results reveal that there exist worst case data patterns in each physical RAM block and cell arrangement. The worst case data pattern occurs when neighboring and victim bit-lines switch to opposite values at the same time. If the bit-line arrangement is known, the test for the CRFs is quite trivial. If there is no knowledge of the internal chip structure, a deterministic pattern cannot be assigned and therefore a generic test method is needed. In this paper, a test algorithm is proposed that exhausts every state of any 3 or 5 bit-lines of a RAM block.Journal of Electronic Testing 04/2006; 22(2):173-187. DOI:10.1007/s10836-006-7486-1 · 0.43 Impact Factor