An Analytical Model for Reliability Evaluation of NoC Architectures.
ABSTRACT This paper proposes an analytical model to assess Reliability Factor of an NoC based System-on-Chip design. Reliability Factor is the probability that faults in the NoC infrastructure can be recovered without any effect on system functionality. The proposed method classifies switch faults of an NoC according to their impact on system functionality. Based on this classification, the contribution of each transient fault lowering the reliability of the NoC is calculated. This model can be used to decide which fault tolerant techniques cause more improvement on system reliability.
- SourceAvailable from: psu.edu[show abstract] [hide abstract]
ABSTRACT: In this article, we discuss design constraints to characterize efficient error recovery mechanisms for the NoC design environment. We explore error control mechanisms at the data link and network layers and present the schemes' architectural details. We investigate the energy efficiency, error protection efficiency, and performance impact of various error recovery mechanisms.IEEE Design and Test of Computers 10/2005; · 1.62 Impact Factor
- [show abstract] [hide abstract]
ABSTRACT: abstraction levels, ranging from electrical to transaction levels, designers can port current simulation methods and tools to networked SoCs NoC libraries, including switches, routers, links, and interfaces, give designers flexible components to complement processor and stor age cores Nevertheless, the usefulness of such libraries will depend heavily on the maturity of the correspond ing synthesis and optimization tools and flows In other words, micronetwork synthesis will enable NoC and SoC design similar to the way logic synthesis made effi cient semicustom design possible in the 1980s Wide adoption of any new design methodology depends on its having a complement of efficient test - of specialized test access mechanisms (TAMs) for dis - - tributing test vectors are very important Moreover, in a communication - centric design environment like that of NoCs, fault tolerance and reliability of the data trans - - mission medium are significant requirements in safety - critical VLSI applications Practical implementation and adoption of the NoC design paradigm faces multiple unresolved issues relat - - ed to design methodology and technology, test strate - gies, dedicated CAD tools, and analysis of architectures - This article discusses these challenges, some proposed solutions, and future directions worth pursuing - Design considerations Although the design process for NoC based systems - - borrows some aspects from the parallel computing domain, it is driven by a significantly different set of con - - straints From the performance perspective, high through - put and low latency are desirable characteristics of MP - SoC platforms However, from a VLSI design perspec - tive, the interconnect architecture's energy dissipationIEEE Design & Test of Computers. 01/2005; 22:404-413.
- [show abstract] [hide abstract]
ABSTRACT: This is the second edition; the first edition was published by Prentice-Hall. The first edition is also available as an Indian edition from Prentice-Hall India. The second edition is also available as Asian edition from John Wiley, Singapore. These cheaper Asian/Indian editions are for use in developing countries.01/2002; John Wiley., ISBN: 0-471-33341-7