Synchronization with timing recovery loop in UHF RFID reader receivers.
ABSTRACT This paper focuses on synchronization of radio frequency identification (RFID) reader receivers, which plays a significant role for stability and efficiency of RFID systems. Performance of RFID reader suffers from a back-link-frequency variation of tags at a maximum of 22% according to widely used RFID standards. A new synchronization scheme employing timing recovery loop in RFID Reader Receivers is presented to solve the problem with less hardware cost. Simulation results give an improved performance compared with conventional schemes. The design is implemented on Xilinx Spartan-3E FPGA and function is verified on our RFID test platform.
Conference Paper: A New Architecture of UHF RFID Digital Receiver for SoC Implementation[Show abstract] [Hide abstract]
ABSTRACT: A new architecture of UHF (ultra high frequency) RFID (radio frequency identification) digital receiver for SoC (system-on-chip) implementation is presented in this paper. For the system requirements, the design uses a unique two-stage correlation algorithm to estimate the frequency of the received data which may have large frequency deviation and also to achieve fast data decoding. Considering the single chip integration, we optimize the implementation for both low hardware cost and quick response. The function of the design is verified through FPGA implementation on Altera StratixII EP2S60 with great performance and its chip design used the SMIC 0.18mum process along with other parts of the UHF RFID interrogator chip.Wireless Communications and Networking Conference, 2007.WCNC 2007. IEEE; 04/2007
Conference Paper: Advanced synchronisation and decoding in RFID reader receivers[Show abstract] [Hide abstract]
ABSTRACT: This paper focuses on one of the major challenges in RFID reader receivers, namely the data synchronisation and decoding at the RFID reader. According to the most widely used RFID standards, the data rate in RFID tag to reader communications is subject to variations within more than one decade, and may deviate from its nominal frequency up to 22%. This results in strong difficulties in synchronising and decoding this data at the receiver of the RFID reader. In order to achieve synchronisation and decoding, a sophisticated algorithm based on correlations is presented. The algorithm is optimised in terms of resource consumption to be processed on an FPGA or ASIC. Implementation details are presented as well as measurements, showing the performance of the receiver.Radio and Wireless Symposium, 2009. RWS '09. IEEE; 02/2009
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ABSTRACT: For pt.I, see ibid., vol.41, no.3, p.502-208 (1993). Properties of a specific class of interpolators that are based upon polynomials are discussed. Several implementations are described, one of which is particularly convenient in practical hardware. Simulations demonstrate that simple interpolators give excellent performance. In many cases, two-point, linear interpolation is adequate. If better performance is needed, classical four-point, third-order polynomials could be used. Better yet, a novel four-point interpolating filter with piecewise-parabolic impulse response can have performance superior to that of the standard cubic interpolator and still be implemented much more simply. The NCO-based control method presented in Part I is shown to be equivalent to a conventional phase locked loop and its operation is verified by simulationIEEE Transactions on Communications 07/1993; 41(6-41):998 - 1008. DOI:10.1109/26.231921 · 1.99 Impact Factor