Conference Paper

Hierarchical Graph: A New Cost Effective Architecture for Network on Chip.

DOI: 10.1007/11596356_33 Conference: Embedded and Ubiquitous Computing - EUC 2005, International Conference EUC 2005, Nagasaki, Japan, December 6-9, 2005, Proceedings
Source: DBLP

ABSTRACT We purposed a new Network on Chip (NoC) architecture called Hierarchical Graph. The most interesting feature of this novel ar- chitecture is its simple implementation process. Furthermore, the flexible structure of this topology makes it suitable for use in application specified chips. To benchmark the suggested architecture with existing ones, basic models of physical implementation have been extracted and simulated using NS-2. The results compared with the common used architecture Mesh show that HG has better performance, especially in local traffics and high loads.

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    ABSTRACT: The Network on Chip (NoC) paradigm is rapidly replacing bus based System on Chip (SoC) designs due to their inherent disadvantages such as non-scalability, saturation and congestion. Currently very few tools are available for the simulation and evaluation of on-chip architectures. This study proposes a generic object oriented model for performance evaluation of on-chip interconnect architectures and algorithms. The generic nature of the proposed model can help the researchers in evaluation of any kind of on-chip switching networks. The model was applied on 2D-Mesh and 2D-Diagonal-Mesh on-chip switching networks for verification and selection of best out of both the analyzed architectures. The results show the superiority of 2D-Diagonal-Mesh over 2D-Mesh in terms of average packet delay.
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    ABSTRACT: Networks-on-chip (NoC), a new system on chip (SoC) paradigm, has become a great focus of research by many groups during the last few years. Among all the NoC architectures that have been proposed until now, 2D-Mesh has proved to be the best architecture for implementation due to its regular and simple intercon- nection structure. In this paper, we propose a new interconnect architecture called 2D-diagonal mesh (2DDgl-Mesh) for on-chip communication. The 2DDgl- Mesh is almost similar to traditional 2D-Mesh in aspects of cost, area, and implementation, but it can outperform the later in delay. The both architectures are compared by using NS-2 (a network simulator) and CINSIM (a component based interconnection simulator) under the same traffic models and parametric conditions. The results of comparison show that under the proposed architecture, the packets can almost always be routed to their destinations in less time. In addition, our archi- tecture can sometimes perform better than 2D-Mesh in drop ratio for special fixed traffic models. issues. Moreover, long wire delays, reusability, less modularity, and scalability issues have been added to the problems of current bus-based SoCs. Consequently, more modular and scalable design methodologies(2)-(4) have been proposed, known as network on chip (NoC), a new SoC paradigm. The use of globally asynchronous locally synchronous concept in NoCs has disintegrated the design of resources from the rest of the network. Its use could enhance the scalability, modularity, and reusability of IP. Design and selection of appropriate architectures for on-chip communication take a key role in the design and implementation of the complete platform for NoC. Different on-chip interconnect architectures were proposed, evaluated, or analyzed in (5)-(8). Among all the NoC architectures presented until now, 2D-Mesh has proved to be the best architecture in terms of implementation due to its regular and simple interconnection structure. 2D-Mesh architecture is also more compatible with ultra deep submicron fabrication technologies. In this paper, we propose a new interconnect architecture, named as 2D-diagonal mesh (2DDgl-Mesh), which has similarities of traditional 2D-Mesh but can perform better than the later in delay and sometimes in drop ratio too.
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    ABSTRACT: In this paper we present the basic ideas behind the development of our novel ring based network-on-chip (NoC) architecture, called ldquoCoronardquo. To achieve minimum hop count, shortest path routing has been applied. Consequently, this ends in average latency reduction (averagely 45%). NS-2 tool is utilized to estimate average latency and packet drop in Corona and 2D mesh with localized and non-localized traffic scenarios. The power consumption of Corona and 2D mesh have been analyzed with LUNA framework. Also, the power consumption is reduced averagely in Corona in comparison to 2D mesh 21% and 29% for localized and non-localized traffic scenarios.


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