Exploiting Register-Usage for Saving Register-File Energy in Embedded Processors.
ABSTRACT Low power register file design plays an important role in an embedded processor. In this paper, we exploit register-usage
in a program to find out unused registers, and turn these unused registers into low power mode by annotating power-controlling
instructions. The whole work is performed by applying the hardware/software co-design principle. For the hardware part, we
propose a voltage-scaling control logic to supply voltages for each register. For the software part, we propose a power-controlling-code
annotation approach to determine the voltage scaling behavior for each register. Simulation results show that the proposed
approach outperforms the other related approaches in terms of the energy-delay product.
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Conference Proceeding: On reducing register pressure and energy in multiple-banked register files[show abstract] [hide abstract]
ABSTRACT: The storage for speculative values in superscalar processors is one of the main sources of complexity and power dissipation. We present a novel technique to reduce register requirements as well as their dynamic and static power dissipation that is based on delaying the dispatch of instructions while minimizing its impact on performance. The proposed technique outperforms previous schemes in both performance and power savings. With only 1.77% IPC loss, the mechanism achieves more than 13% dynamic and 15% static extra power savings in the integer rename buffers and more than 9% dynamic and 10% static extra power savings in the FP rename buffers. Significant power savings are also achieved if the processor uses a physical register file for both committed and noncommitted values instead of rename buffers. Additionally the register requirements are reduced by more than 18% and 13% for integer and FP programs respectively.Computer Design, 2003. Proceedings. 21st International Conference on; 11/2003
Conference Proceeding: MiBench: A free, commercially representative embedded benchmark suite[show abstract] [hide abstract]
ABSTRACT: This paper examines a set of commercially representative embedded programs and compares them to an existing benchmark suite, SPEC2000. A new version of SimpleScalar that has been adapted to the ARM instruction set is used to characterize the performance of the benchmarks using configurations similar to current and next generation embedded processors. Several characteristics distinguish the representative embedded programs from the existing SPEC benchmarks including instruction distribution, memory behavior, and available parallelism. The embedded benchmarks, called MiBench, are freely available to all researchers.Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop on; 01/2002
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ABSTRACT: Power dissipation and thermal issues are increasingly significant in modern processors. As a result, it is crucial that power/performance tradeoffs be made more visible to chip architects and even compiler writers, in addition to circuit designers. Most existing power analysis tools achieve high accuracy by calculating power estimates for designs only after layout or floorplanning are complete In addition to being available only late in the design process, such tools are often quite slow, which compounds the difficulty of running them for a large space of design possibilities.03/2001;