Conference Paper

An Application-Level Dependability Analysis Framework for Embedded Systems

DOI: 10.1109/DFT.2011.25 Conference: 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011, Vancouver, BC, Canada, October 3-5, 2011
Source: DBLP


This paper presents a framework for an in-depth analysis of transient faults in microprocessor-based embedded systems. The framework is based on a debug-like mechanism supporting an interpretation and analysis of the system behavior from an application point of view, in terms of function execution flow and passed/returned parameters. The framework offers a highly-customizable fault/error debug and classification approach, based on such application-level information, aimed at supporting the designer in the evaluation and tuning of the system dependability-related properties. We present an implementation of the proposed framework within a state-of-the-art fault injection environment for SystemC transaction-level multiprocessor specifications, and we show that the approach can be ported also in other environments. An experimental session considering an embedded system based on a processor highlights the benefits of the proposed approach.

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    ABSTRACT: To support the reliability assessment of safety-relevant distributed automotive systems and reduce its complexity, this paper presents a novel approach that extends virtual prototyping towards error effect simulation. Besides the common functional and timed system simulation, error injection is used to stress error tolerance mechanisms. A quantitative assessment of the overall system reliability is performed by observing the system reactions and identifying incorrect system behavior. To foster the industrial application, the analysis is integrated in a model-based design flow, starting at the modeling level to assemble and parameterize the virtual prototype and to configure the analysis. The feasibility of the proposed approach is demonstrated by analyzing a representative safety-relevant automotive use case.
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    ABSTRACT: This paper presents a methodology for the system-level dependability analysis of multiprocessor embedded systems. The methodology is based on fault injection and features an error analysis approach offering to the designer the possibility to specify custom monitoring and classification actions at both application and architecture levels. In particular, a debug-like mechanism offers the possibility to interpret architectural raw data observed during the simulation at application level with a function call/return granularity, thus offering the possibility to analyze the propagation of the errors in the various functionalities of the executed application. A framework for automating the proposed methodology has been implemented within a state-of-the-art SystemC/TLM simulation platform for multiprocessor specifications provided with a fault injection engine. The effectiveness of the methodology has been demonstrated in two different case studies, showing how the proposed approach is able to produce an accurate dependability report highlighting the criticalities in both the architecture and the application of the system under design.
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