Conference Paper

Templated-Based Asynchronous Design for Testable and Fail-Safe Operation.

DOI: 10.1109/DFT.2011.63 Conference: 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011, Vancouver, BC, Canada, October 3-5, 2011
Source: DBLP

ABSTRACT Asynchronous design is a promising alternative for emerging technologies facing extreme parameter variation, severe timing/clock skew and power consumption issues. However, the complexity in design and test is one of the major obstacles for the widespread use of asynchronous circuits in digital design. Circuits utilizing templates are often implemented to mitigate the design complexity of an asynchronous circuit. One of the most commonly used pre-designed templates is the so-called Pre-Charged Full Buffer (PCFB), however, when testing template-based designs, most of the faults are undetectable by using conventional methods. In this paper, the PCFB template is designed such that faults always result in three scenarios (deadlock, token generation and dropping) for ease of detection, its operation and the new design of the hardware required for testability are described in detail. It is analytically shown that under a model that includes all single stuck-at faults, the new template (as characterized by novel features in its design) accomplishes ease of testability as well as online detection and fail-safe circuit operation. 100% coverage of single faults is accomplished. Simulation results for benchmark circuits are provided.

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