Templated-Based Asynchronous Design for Testable and Fail-Safe Operation.
ABSTRACT Asynchronous design is a promising alternative for emerging technologies facing extreme parameter variation, severe timing/clock skew and power consumption issues. However, the complexity in design and test is one of the major obstacles for the widespread use of asynchronous circuits in digital design. Circuits utilizing templates are often implemented to mitigate the design complexity of an asynchronous circuit. One of the most commonly used pre-designed templates is the so-called Pre-Charged Full Buffer (PCFB), however, when testing template-based designs, most of the faults are undetectable by using conventional methods. In this paper, the PCFB template is designed such that faults always result in three scenarios (deadlock, token generation and dropping) for ease of detection, its operation and the new design of the hardware required for testability are described in detail. It is analytically shown that under a model that includes all single stuck-at faults, the new template (as characterized by novel features in its design) accomplishes ease of testability as well as online detection and fail-safe circuit operation. 100% coverage of single faults is accomplished. Simulation results for benchmark circuits are provided.
- SourceAvailable from: psu.edu[Show abstract] [Hide abstract]
ABSTRACT: The design of an asynchronous clone of a MIPS R3000 microprocessor is presented. In 0:6m CMOS, we expect performance close to 280 MIPS, for a power consumption of 7 W. The paper describes the structure of a high-performance asynchronous pipeline, in particular precise exceptions, pipelined caches, arithmetic, and registers, and the circuit techniques developed to achieve high throughput. 1 Introduction This paper describes the architectural algorithms and circuit techniques used in the design of an asynchronous MIPS R3000 microprocessor. The project has two main goals. First, we are investigating issues in asynchronous processor architecture that we have not tackled in the Caltech Asynchronous Microprocessor : caches, precise exceptions, register bypassing, branch-delay slot and branch prediction. Secondly, we are developing new techniques for asynchronous digital VLSI---based on very fine pipelining---that can meet high throughput requirements without sacrificing the low-power ad...07/1999;
- [Show abstract] [Hide abstract]
ABSTRACT: In this paper, we show how to use Verilog HDL along with PLI (Programming Language Interface) to model asynchronous circuits at the behavioral level by implementing CSP (Communicating Sequential Processes) language constructs. Channels and communicating actions are modeled in Verilog HDL as abstract actions.Design Automation Conference, 2003. Proceedings; 07/2003
Conference Paper: Off-line testing of asynchronous circuits[Show abstract] [Hide abstract]
ABSTRACT: A new technique to test asynchronous circuits obtained by direct mapping technique from I-safe Petri nets is proposed. Low-level physical faults in the cells implementing Petri net places are analysed and mapped into high-level specification, a Petri net. A "pseudo clock" is used to handle hazards and activate faults which exhibit themselves only under particular arrangements. Asynchronous circuit obtained by direct mapping technique can be made 100% testable for stuck-at-faults by implementing testability features. An algorithm to insert testability features and generate test sequences is presented using a benchmark.VLSI Design, 2005. 18th International Conference on; 02/2005