Conference Paper

A Parallel Branching Program Machine for Emulation of Sequential Circuits.

DOI: 10.1007/978-3-642-00641-8_26 Conference: Reconfigurable Computing: Architectures, Tools and Applications, 5th International Workshop, ARC 2009, Karlsruhe, Germany, March 16-18, 2009. Proceedings
Source: DBLP

ABSTRACT The parallel branching program machine (PBM128) consists of 128 branching program machines (BMs) and a programmable interconnection.
To represent logic functions on BMs, we use quaternary decision diagrams. To evaluate functions, we use 3-address quaternary
branch instructions. We emulated many benchmark circuits on PBM128, and compared its memory size and computation time with
the Intel’s Core2Duo microprocessor. PBM128 requires approximately quarter of the memory for the Core2Duo, and is 21.4-96.1
times faster than the Core2Duo.

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    ABSTRACT: A branching program machine (BM) is a special-purpose processor that uses only two kinds of in- structions: Branch and output instructions. Thus, the architecture for the BM is much simpler than that for a general-purpose microprocessor (MPU). Since the BM uses the dedicated instructions for a special-purpose appli- cation, it is faster than the MPU. This paper presents a packet classifier using a parallel BMs (PBM). To reduce computation time and code size, first, a set of rules for packet classifier is partitioned into subsets. Then, the PBM evaluates them in parallel. Also, the paper shows a method to estimate the necessary number of BMs to realize a given packet classifier. We implemented the PBM32, a system using 32 BMs, on an FPGA, and compared it with the Intel's Core2Duo@1.2GHz microprocessor. The PBM32 is 8.1-11.1 times faster than the Core2Duo, and the PBM32 requries only 0.2-10.3 percent of the memory for the Core2Duo.
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