Conference Paper

Algorithm and VLSI architecture for linear MMSE detection in MIMO-OFDM systems

Integrated Syst. Lab., ETH, Zurich
DOI: 10.1109/ISCAS.2006.1693531 Conference: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece
Source: DBLP

ABSTRACT The paper describes an algorithm and a corresponding VLSI architecture for the implementation of linear MMSE detection in packet-based MIMO-OFDM communication systems. The advantages of the presented receiver architecture are low latency, high-throughput, and efficient resource utilization, since the hardware required for the computation of the MMSE estimators is reused for the detection. The algorithm also supports the extraction of soft information for channel decoding

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