Conference Paper

Hierarchy-aware and area-efficient test infrastructure design for core-based system chips.

DOI: 10.1145/1131561 Conference: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006
Source: DBLP

ABSTRACT Multiple levels of design hierarchy are common in current- generation system-on-chip (SOC) integrated circuits. However, most prior work on test access mechanism (TAM) optimization and test scheduling is based on a flattened design hierarchy. We investigate hierarchy-aware test infrastructure design, wherein wrapper/TAM optimization and test scheduling are carried out for hierarchical SOCs for two practical design scenarios. In the first scenario, the wrapper and TAM implementation for the em- bedded child cores in hierarchical (parent) cores are delivered in a hard form by the core provider. In the second scenario, the wrapper and TAM architecture of the child cores embedded in the parent cores are implemented by the system integrator. Ex- perimental results are presented for the ITC'02 SOC test bench- marks. test schedules designed for non-hierarchical SOCs are typically not valid for SOCs with hierarchical cores. The hierarchy im- poses a number of constraints on the manner in which tests must be applied to parent cores and their embedded child cores (8); hierarchy-oblivious methods make no attempt to satisfy these constraints. In this paper, we describe a test infrastructure design approach for hierarchical SOCs; our approach is based on hierarchy-aware wrapper design for parent cores, TAM optimization techniques for the SOC and the parent cores, and chip-level test scheduling. We consider two different test infrastructure design scenarios. In Scenario 1, we assume that the wrappers and TAM architectures for the child cores are given and fixed (hard), while the wrappers and TAM architectures for the parent cores are to be determined by our approach (soft). In Scenario 2, the wrapper and TAM for both parent and child cores are assumed to be soft. The sequel of this paper is organized as follows. In Section 2, we review the limitations of prior work. In Section 3, we discuss various DfT techniques that can be used to reduce test length. Section 4 describes our approach for Scenario 1, while Section 5 addresses Scenario 2. We derive lower bounds on the test time in Section 6. In Section 7, we present test application times and lower bounds for the ITC'02 SOC test benchmarks (5). Finally, Section 8 concludes the paper.

0 Bookmarks
 · 
59 Views
  • Source
  • [Show abstract] [Hide abstract]
    ABSTRACT: A cost effective system-on-a-chip (SOC) test strongly hinges on the parallel independent test of SOC cores, which can only be ensured through proper core isolation techniques. Whereas a core isolation mechanism can provide controllability and observability at the core I/O interface, its implementation may have various implications on area, functional timing, test time and data volume, and at-speed coverage on the core interface. In this paper, we provide an in-depth analysis of the soft core isolation problem by covering a wide spectrum of techniques ranging from the utilization of only functional registers to the utilization of only wrapper cells. We model the generalized problem of finding the minimum number of isolation registers, in the form of a mixture of functional registers and wrapper cells, by mapping the problem onto the maximum Boolean satisfiability problem; by utilizing the key findings in this mapping, we implement a computationally efficient heuristic for selecting a subset of core I/Os, on which wrapper cell insertion minimizes the total number of interface registers. Finally, we demonstrate the application of this heuristic, with area and performance constraints also accounted for, delivering a wide spectrum of tradeoff points for isolating a soft core.
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 09/2008; · 1.09 Impact Factor
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: Modular SOC testing offers numerous benefits that include test power reduction, ease of timing closure, and test re-use among many others. While all these benefits have been emphasized by researchers, the test time and data volume comparisons has been mostly constrained within the context of modular SOC testing only, by comparing the impact of various different modular SOC testing techniques to each other. In this paper, we provide a theoretical test data volume analysis that compares the monolithic test of a flattened design with the same design tested in a modular manner; we present numerous experiments that gauge the magnitude of this benefit. We show that the test data volume reduction delivered by modular SOC testing directly hinges on the test pattern count variation across different modules, and that this reduction can exceed 99% in the SOC benchmarks that we have experimented with.
    Design, Automation and Test in Europe, 2008. DATE '08; 04/2008

Full-text (2 Sources)

View
13 Downloads
Available from
May 27, 2014