Conference Paper
Performance analysis of greedy shapers in realtime systems.
DOI: 10.1109/DATE.2006.243801 Conference: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 610, 2006
Source: DBLP

Conference Paper: An Interface Algebra for Estimating WorstCase Traversal Times in Component Networks.
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ABSTRACT: Interfacebased design relies on the idea that different components of a system may be developed independently and a system designer can connect them together only if their interfaces match, without knowing the details of their internals. In this paper we propose an interface algebra for analyzing networks of embedded systems components. The goal is to be able to compute worstcase traversal times and verify their compliance to provided deadlines in such component networks in an incremental manner, i.e., as and when new components are added or removed from the network. We lay the basic groundwork for this algebra and show its utility through an illustrative example.Leveraging Applications of Formal Methods, Verification, and Validation  4th International Symposium on Leveraging Applications, ISoLA 2010, Heraklion, Crete, Greece, October 1821, 2010, Proceedings, Part I; 01/2010  [Show abstract] [Hide abstract]
ABSTRACT: The reliability of multiprocessor systemonchips (MPSoCs) is nowadays threatened by high chip temperatures leading to longterm reliability concerns and shortterm functional errors. High chip temperatures might not only cause potential deadline violations, but also increase cooling costs and leakage power. Proactive thermalaware allocation and scheduling techniques that avoid thermal emergencies are promising techniques to reduce the peak temperature of an MPSoC. However, calculating the peak temperature of hundreds of design alternatives during design space exploration is timeconsuming, in particular for unknown input patterns and data. In this paper, we address this challenge and present a fast analytic method to calculate a nontrivial upper bound on the maximum temperature of a multicore realtime system with nondeterministic workload. The considered thermal model is able to address various thermal effects like heat exchange between neighboring cores and temperaturedependent leakage power. Afterwards, we integrate the proposed thermal analysis method into a designspace exploration framework to optimize the task to processing component assignment. Finally, we apply the proposed method in various case studies to explore thermal hot spots and to optimize the task to processing component assignment.Journal of Electronic Testing: Theory and Applications. 08/2013; 29(4):521535. 
Conference Paper: WorstCase Temperature Analysis for Different Resource Availabilities: A Case Study.
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ABSTRACT: With threedimensional chip integration, the heat dissipation per unit area increases rapidly and may result in high onchip temperatures. Realtime constraints cannot be guaranteed anymore as exceeding a certain threshold temperature can immediately reduce the systems reliability and performance. Dynamic thermal management methods are promising methods to prevent the system from overheating. However, when designing modern realtime systems that make use of such thermal management techniques, the designer has to be aware of their effect on the maximum possible temperature of the system. This paper proposes an analytic framework to calculate the worstcase temperature of a system with general resource availabilities. The event and resource model is based on realtime and network calculus so that the method is able to handle a broad range of uncertainties in terms of task arrivals and available computational power. In various case studies, the proposed framework is applied to an advanced multimedia system to analyze the impact of dynamic frequency scaling and thermalaware scheduling techniques on the worstcase temperature of an embedded realtime system.Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation  21st International Workshop, PATMOS 2011, Madrid, Spain, September 2629, 2011. Proceedings; 01/2011
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