Conference Paper

Adaptive chip-package thermal analysis for synthesis and design.

DOI: 10.1145/1131720 Conference: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006
Source: DBLP

ABSTRACT Ever-increasing integrated circuit (IC) power densities and peak temperatures threaten reliability, performance, and economical cool- ing. To address these challenges, thermal analysis must be embedded within IC synthesis. However, detailed thermal analysis requires ac- curate three-dimensional chip-package heat flow analysis. This has typically been based on numerical methods that are too computation- ally intensive for numerous repeated applications during synthesis or design. Thermal analysis techniques must be both accurate and fast for use in IC synthesis. This article presents a novel, accurate, incremental, self-adaptive, chip-package thermal analysis technique, called ISAC, for use in IC synthesis and design. It is common for IC temperature variation to strongly depend on position and time. ISAC dynamically adapts spatial and temporal modeling granularity to achieve high efficiency while maintaining accuracy. Both steady-state and dynamic thermal analysis are accelerated by the proposed heterogeneous spatial res- olution adaptation and temporally decoupled element time marching techniques. Each technique enables orders of magnitude improvement in performance while preserving accuracy when compared with other state-of-the-art adaptive steady-state and dynamic IC thermal analysis techniques. Experimental results indicate that these improvements are sufficient to make accurate dynamic and static thermal analysis prac- tical within the inner loops of IC synthesis algorithms. ISAC has been validated against reliable commercial thermal analysis tools using in- dustrial and academic synthesis test cases and chip designs. It has been implemented as a software package suitable for integration in IC synthesis and design flows and has been publicly released.

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