Conference Paper

Customization of application specific heterogeneous multi-pipeline processors.

DOI: 10.1145/1131693 Conference: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006
Source: DBLP

ABSTRACT In this paper we propose Application Specific Instruction Set Processors with heterogeneous multiple pipelines to efficiently exploit the available parallelism at instruction level. We have developed a design system based on the Thumb processor architecture. Given an application specified in C language, the design system can generate a processor with a number of pipelines specifically suitable to the application, and the parallel code associated with the processor. Each pipeline in such a processor is customized, and implements its own special instruction set so that the instructions can be executed in parallel with low hardware overhead. Our simulations and experiments with a group of benchmarks, largely from Mibench suite, show that on average, 77% performance improvement can be achieved compared to a single pipeline ASIP, with the overheads of 49% on area, 51% on leakage power, 17% on switching activity, and 69% on code size.

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    • "We generated codes with and without loop unrolling. Both types of assembly codes were scheduled into a number of pipelines based on the available ILP using the algorithm specified in [3]. The scheduled code was assembled into binary. "
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    • "The approach focuses on encoding instructions for opcode field, assuming operand field length for each instruction is given. These approaches are not tailored to our target processors proposed in [16]. The techniques presented in this paper exploits the unique architectural features of our target ASIP, where each pipeline has different control unit for different set of instructions. "
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