Fast Start-up for Spartan-6 FPGAs using Dynamic Partial Reconfiguration.
ABSTRACT This paper introduces the first available tool flow for Dynamic Partial Reconfiguration on the Spartan-6 family. In addition, the paper proposes a new configuration method called Fast Start-up targeting modern FPGA architectures, where the FPGA is configured in two-steps, instead of using a single (monolithic) full device configuration. In this novel approach, only the timing-critical modules are loaded at power-up using the first high-priority bitstream, while the non-timing critical modules are loaded afterwards. This two-step or prioritized FPGA start-up is used in order to meet the extremely tight startup timing specifications found in many modern applications, like PCI-express or automotive applications. Finally, the developed tool flow and methods for Fast Start-up have been used and tested to implement a CAN-based automotive ECU on a Spartan-6 evaluation board (i.e., SP605). By using this novel approach, it was possible to decrease the initial bitstream size and hence, achieve a configuration time speed-up of up to 4.5×, when compared to a standard configuration solution.
- [Show abstract] [Hide abstract]
ABSTRACT: The sequential execution of processing elements by time-multiplexing FPGA resources using single-island partial reconfiguration allows for resource-efficient designs in comparison to static FPGA implementations. Designing a processing chain for such a system requires the chain to be partitioned into reconfigurable modules, which can be sequentially executed. For this task, we will present an approach to partition an existing digital signal processing chain into separate modules with the goal to obtain a balanced logic occupation. Furthermore, we will show how the overhead of context switching can be reduced by frame-aware data processing and we will introduce a context-annotation scheme for synchronous data flow graphs. After applying our findings to a reconfigurable digital audio broadcasting receiver and quantifying the benefits and drawbacks of time-multiplexed execution, we will finally show that the time-multiplexed execution of receiver components decreases the resource consumption as compared to the static design.Design and Architectures for Signal and Image Processing (DASIP), 2012 Conference on; 01/2012
Conference Paper: Embedded Systems Start-Up under Timing Constraints on Modern FPGAs.[Show abstract] [Hide abstract]
ABSTRACT: In this paper we present novel techniques, methods and tool flows that enable embedded systems implemented on FPGAs to start-up under tight timing constraints (i.e., hard deadlines). Meeting the application deadline is achieved by exploiting the FPGA programmability in order to implement a two-stage system start-up approach, as well as a suitable memory hierarchy. This reduces the FPGA configuration time as well as the startup time of the embedded software. Thereby the start-up time for timing-critical parts of a design neither dependent on the complexity nor on the start-up time of the complete system. An automotive case study is used to demonstrate the feasibility and quantify the benefits of the proposed approach.International Conference on Field Programmable Logic and Applications, FPL 2011, September 5-7, Chania, Crete, Greece; 01/2011