Maximum circuit activity estimation using pseudo-boolean satisfiability.

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Maximum Circuit Activity Estimation Using
Pseudo-Boolean Satisfiability
Hratch Mangassarian1
Andreas Veneris1,2
Sean Safarpour1
Farid N. Najm1
Magdy S. Abadir3
Abstract—Disproportionate instantaneous power dissipation
may result in unexpected power supply voltage fluctuations and
permanent circuit damage. Therefore, estimation of maximum
instantaneous power is crucial for the reliability assessment of
VLSI chips. Circuit activity and consequently power dissipation
in CMOS circuits are highly input-pattern dependent, making the
problem of maximum power estimation computationally hard.
This work proposes a novel pseudo-boolean satisfiability based
method that reports the exact input sequence maximizing circuit
activity in combinational and sequential circuits. The method
is also extended to take multiple gate transitions into account
by integrating delay information into the pseudo-boolean opti-
mization problem. An extensive suite of experiments on ISCAS85
and ISCAS89 circuits confirms the efficiency and robustness of
the approach compared to simulation based techniques and en-
courages further research for low-power solutions using boolean
satisfiability.
I. INTRODUCTION
In the nanometer VLSI era, reliability analysis of digital VLSI
circuits is taking a significant share of the design process. In view of
the roughly doubling component failure rate for every 10oC increase
in operating temperature [1], overheating caused by excessive power
dissipation can degrade performance and reduce chip lifetime [2].
Large instantaneous power dissipation can also lead to a temporary
voltage drop on power supply lines, which can result in soft errors [3].
Hence, accurate estimation of maximum peak power is vital to the
reliability analysis of a circuit.
Dynamic power in CMOS circuits is a nontrivial function of
clock frequency, technology parameters, gate capacitances and delays,
circuit topology and primary input vectors. With everything else
held constant, the pair of consecutive primary inputs that maximizes
the switched capacitance in the circuit also maximizes dynamic
peak power. Finding this pair among an exponential number of
possibilities, or equivalently finding the associated circuit activity, is
a combinatorial optimization problem whose corresponding decision
problem is NP-complete.
Recent advances [13, 14, 15] and ongoing research in boolean
satisfiability (SAT) have made it an attractive tool for solving theo-
retically intractable problems in VLSI CAD, in areas such as test-
ing [16], verification [20], debugging [21] and physical design [22].
Furthermore, any improvement to the state-of-the-art in SAT solving
immediately benefits all SAT based solutions.
This work proposes a pseudo-boolean satisfiability (PB-SAT)
based method for generating tight lower bounds on maximum circuit
activity per clock cycle. Given enough time, the method is guaranteed
to find the exact input sequence that maximizes the given circuit
activity model. The described framework is applicable to both com-
binational and sequential circuits. It is also extended to take glitches
into account by integrating delay into the pseudo-boolean (PB) opti-
mization problem. The competitive experimental results in this paper
confirm the robustness of SAT in low-power analysis techniques.
Coupled with the wide-ranging modeling flexibility offered by SAT,
this encourages further research in the use of SAT as a platform to
solve other low-power problems.
The rest of the paper is organized as follows. Section 2 presents
previous work. Section 3 contains background information on SAT
and PB-SAT theory. Section 4 briefly discusses assumptions and
1University of Toronto, ECE Department, Toronto, ON M5S 3G4 ({hratch,
veneris, sean, najm}@eecg.toronto.edu)
2University of Toronto, CS Department, Toronto, ON M5S 3G4
3FreescaleSemiconductor,
({M.Abadir}@freescale.com)
Inc., Austin, TX78729
preliminaries. Section 5 gives the PB formulations for the maximum
activity problem in combinational and sequential circuits. Section 6
extends the method to incorporate unit gate delay. Section 7 presents
optimizations and heuristics. Section 8 contains experiments and
Section 9 concludes the paper.
II. PREVIOUS WORK
Several techniques have been proposed to estimate the maximum
peak power dissipation of a CMOS circuit [6-12]. An analogous
problem is that of finding the maximum instantaneous current [3-5].
In [3, 4], a loose upper bound on the maximum instantaneous current
is generated in linear time by propagating the signal uncertainty
through the circuit. The upper bound is subsequently tightened using a
branch-and-bound algorithm by considering spatial signal correlations
at gate outputs. Extending the characterization of signal correlations
from [3, 4] and exploiting mutually exclusive gate switching, the
authors in [5] manage to generate tighter upper bounds. However, for
larger circuits, the gap between the generated upper bounds and lower
bounds obtained using random simulations can remain considerable.
In [6], the authors present an Automatic Test Pattern Generation
(ATPG) based greedy algorithm that strives to maximize the fanout-
weighted gate flips of a circuit. In [7], the method is extended to cover
sequential circuits as well as glitches. A continuous optimization
method is put forward in [8], which treats the boolean input space
as a real-valued vector space and makes use of a gradient based
heuristic to estimate the maximum power. A genetic search algorithm
proposed in [9, 10] generates more robust lower bounds. In [11],
the authors describe a statistical method that draws on the theory of
Asymptotic Extreme Order Statistics. The probability distribution of
the maximum power in a random sample of fixed size is computed.
The largest power value with a non-zero probability is estimated to
determine the maximum peak power.
The approach that is closest to this work is given in [12], where the
power dissipation of a circuit is modeled as a multi-output Boolean
function in terms of the primary inputs. A disjoint cover enumeration
as well as a branch-and-bound algorithm are used to maximize
the number of weighted gate transitions. An approximation strategy
for upper bounding maximum power is also proposed. However,
the described techniques can become computationally expensive.
Furthermore, sequential circuits are not covered.
III. BACKGROUND
A. Boolean Satisfiability
A propositional logic formula Φ is a logic function over a set of
boolean variables linked by boolean connectives such as ¬ (negation),
· (conjunction), + (disjunction), → (implication) and ↔ (equiv-
alence). Φ is said to be satisfiable or SAT if it has a satisfying
assignment: a truth assignment Π of its variables that causes it to
evaluate to true, denoted as Π |= Φ. Otherwise, Φ is said to
be unsatisfiable or UNSAT. The problem of boolean satisfiability
consists of determining whether Φ is SAT. In modern SAT solvers,
the logic formula Φ is given in Conjunctive Normal Form (CNF) as a
conjunction of clauses where each clause is a disjunction of literals.
A literal is an instance of a variable or its negation. In order for a
formula to be SAT, at least one literal in each clause must evaluate
to true. For example, the CNF formula given in (1) is SAT because
{a = 1,b = 0,c = 1} |= Φ.
Φ = (a + b) · (a + b + c) · (c)
A logic circuit can be converted to a CNF formula in linear
time [16], such that there is a one-to-one correspondence between the
variables of the generated CNF formula and the gate outputs of the
corresponding circuit, and such that satisfying variable assignments
(1)

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in the CNF formula correspond to valid gate output values in the
circuit. Hence, a circuit and its corresponding SAT formulation are
often referred to interchangeably in this paper.
Modern SAT solvers [13, 14, 15] are able to solve large SAT
problems with millions of clauses and hundreds of thousands of
variables by utilizing advanced branch-and-bound procedures such
as intelligent decision making, conflict based learning, and non-
chronological backtracking. During the solving procedure, SAT
solvers strive to prune parts of the non-solution search-space by
analyzing their mistakes and learning from them by appending
conflict clauses to the original CNF formula. For example, consider
the CNF formula in (1) and suppose that the solver has made the
unsatisfiable variable assignments {a = 0,b = 1,c = 1}. A modern
SAT solver might determine that the real cause of the conflict is the
assignment {a = 0}, and hence add the conflict clause (a) to Φ in
order to force {a = 1}.
B. Pseudo-Boolean Satisfiability
A pseudo-boolean constraint is a generalization of a CNF clause.
A PB constraint over boolean variables {xi}n−1
the form:
n−1
?
where {ci}n
{xi}n−1
constraint where ci = 1 for 0 ≤ i ≤ n.
A coefficient ci is said to be activated if its corresponding literal
li is assigned to true. A PB constraint is said to be satisfied if
(2) holds. A PB formula Ψ is a conjunction of PB constraints. The
problem of pseudo-boolean satisfiability questions the existence of a
truth assignment to {xi}n−1
The pseudo-boolean optimization problem strives to find a satisfi-
able assignment to Ψ that also minimizes a given objective function:
i=0is an inequality of
i=0
cili ≥ cn
(2)
i=0∈ Z and {li}n−1
i=0. I.e., li = xi or li = xi. Note that a CNF clause is a PB
i=0are the literals corresponding to
i=0satisfying all the PB constraints in Ψ.
F(x) =
n−1
?
i=0
dili
(3)
where x =< x0,...,xn−1 > and {di}n−1
For example, given Ψ and F as shown in (4) below, both {a =
1,b = 0,c = 1} and {a = 1,b = 0,c = 0} are satisfying
assignments. However, only the former minimizes F.
Ψ= (2a − 3b ≥ 1) ∧ (a + b + c ≥ 1)
F
There are two types of PB solvers: [18, 19] support PB constraints
natively, while [17] translates the PB-SAT problem into a SAT
problem and runs a state-of-the-art SAT solver [15] on the produced
SAT instance. The latter approach is particularly suited to problems
that are almost “pure” SAT [17] (i.e., consisting of mostly SAT
clauses and relatively few PB constraints), which is the case in
this work. Furthermore, any advancements in SAT solving directly
enhances such a strategy. Optimal translation of PB-SAT constraints
into a set of CNF clauses is currently an area of active research.
The objective function is minimized as follows. The PB-SAT
solver in [17] first runs the SAT solver without considering F(x) in
order to get an initial SAT solution x0, with say F(x0) = k, where
k is the corresponding initial value of the objective function. The new
PB constraint F(x) ≤ k − 1 is subsequently added to the original
problem. The SAT solver runs on the updated CNF formula and this
process is repeated until the problem becomes UNSAT. The solution
corresponding to the last k before the problem becomes UNSAT is
the optimal solution minimizing the objective function.
i=0∈ Z.
=
c − a + 2b
(4)
IV. ASSUMPTIONS AND PRELIMINARIES
In this work, latch-controlled synchronous digital circuits are
considered. Primary inputs (PIs) and flip-flop (FF) outputs can only
switch at the beginning of the clock cycle. This assumption is
considered valid in related previous work as well.
The average dynamic power dissipation of a CMOS circuit is
proportional to the total switched capacitance:
m
?
P ∝
i=0
CiT(gi)
(5)
where m is the number of circuit gates, Ci is the capacitive load on
gate gi and T(gi) is the output transition count of gi per unit time.
Under the assumption that the clock period is sufficiently small,
it is sound to interpret the average dynamic power dissipation over a
clock cycle as the instantaneous dynamic power during that clock
cycle [6-12]. Thus, letting T(gi) in Eq. (5) correspond to the
transition count of gi during a clock cycle, P can be viewed as
the instantaneous dynamic power. In the remainder of this work,
instantaneous dynamic power is simply referred to as power.
The following notation is used throughout this paper. G denotes
the set of gates (|G| = m), I the set of PIs (|I| = n) and S the
set of FFs (|S| = p). FANOUTS(gi) (FANINS(gi)) denotes the set of
fanouts (fanins) of gi. Finally, in all the examples and experiments, it
is assumed that Ci = |FANOUTS(gi)| for internal gates and Ci = 1
for primary output gates.
V. ZERO-DELAY MAXIMUM ACTIVITY COMPUTATION
USING PB-SAT
A. Maximum Activity for Combinational Circuits
Under a zero-delay model, T(gi) becomes a boolean variable
because gi can flip at most once per clock cycle. Accordingly, Eq.
(5) can be rewritten as:
?
where I and I?are consecutively applied PI vectors and gi(X)
denotes the steady-state value of gi given PI vector X.
The problem then translates into finding the pair of consecutive
PI vectors < I∗,I?∗> that maximizes the right-hand-side of Eq. (6)
and therefore P:
< I∗,I?∗>=argmax
<I,I?>∈{0,1}2n
P ∝
m
i=1
Ci
?gi(I) ⊕ gi(I?)?
(6)
m
?
i=1
Ci
?gi(I) ⊕ gi(I?)?
(7)
o2
o1
ˆC
d
b
i1
i2
c
a
i3
(a) Zero-delay gate
switching
C4= 1
C3= 1
C2= 1
C1= 3
C?
C
d?
i?
3
b?
c?
i?
2
i?
1
a?
i2
i1
d
b
N
a
a?
b
b?
c
c?
d
d?
xor1
xor2
xor3
xor4
c
a
i3
(b) Zero-delay PB-SAT formula-
tion
Combinational circuit Fig. 1.
The solving procedure of Eq. (7) relies on the construction of a
new circuit that will be used by the PB-SAT solver. The general
procedure is illustrated with the use of an example. Consider the
problem of finding the pair of PI vectors maximizing power for the
circuit shown in fig. 1(a). First, the original circuit and its PIs are
duplicated as shown in fig. 1(b). Next, every pair of corresponding
gates, gi in C and g?
circuit N. Since gi and g?
xori = gi(I)⊕gi(I?) becomes 1 if and only if the output of gate gi
flips under consecutive input vectors I and I?. The weighted sum of
these XOR outputs,?m
can be transformed to a SAT CNF which is a set of PB constraints,
the following PB optimization problem strives to maximize the right-
hand-side of Eq. (6) and therefore to solve Eq. (7):
iin C?, is fed to an XOR gate, xori, in the new
iperform the same logic function, clearly
i=1Cixori, is equal to the right hand-side-side
of Eq. (6), which should be maximized. Given that the circuit N itself
Ψ=CNF(N)
m
?
F
=
−
i=1
Cixori
(8)
Remark that only the target function F in (8) is not in a pure SAT
format. The PB formula Ψ is simply the CNF of N, which markedly
suits the choice of the PB-SAT solver [17].

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Example 1 Consider the original circuitˆC and the corresponding
construction N shown in Fig. 1. An optimal solution to the associated
PB optimization problem given by (8) is < I∗,I?∗>=<< 0,0,0 >
,< 1,1,1 >>, which amounts to a total switched capacitance of 6
units by flipping all four gate outputs as shown in Fig. 1(a).
B. Maximum Activity for Sequential Circuits
Let δ : {0,1}p× {0,1}n→ {0,1}pdenote the state transition
function of a given sequential circuit. Also, let gi(S,X) denote
the steady-state value of gi given initial state S and PI vector
X. Estimating the peak power per cycle for sequential circuits is
equivalent to finding a triplet < S∗,I∗,I?∗> consisting of an initial
state S and consecutive PI vectors, I and I?, that maximizes the
right-hand-side of Eq. (9):
m
?
i1
i2
P ∝
i=1
Ci
?
gi
?S,I?⊕ gi
?δ(S,I),I???
(9)
a
0
s1
i1
i2
i3
ˆC
o1
cb
d
(a) Zero-delay switching
a?
a
s1
a
i?
3
C
d
i3
i?
1
c
N
b?
i?
2
d?
C1= 2
C2= 1
C3= 1
C4= 1
xor4
xor3
xor2
xor1
d
c?c
b?b
a?a
b
c?
d?
C?
(b) Zero-delay PB-SAT formulation
Sequential circuit Fig. 2.
The general solving procedure for this problem is illustrated with
the use of an example. Consider the sequential circuitˆC shown
in Fig. 2(a). First, FF inputs (outputs) are transformed into circuit
pseudo-outputs (pseudo-inputs). This full-scanned circuit C is sub-
sequently duplicated similarly to the combinational case. Moreover,
the pseudo-outputs of the first time-frame C are connected to the
pseudo-inputs of the second time-frame C?as shown in Fig. 2(b).
This iterative logic array (ILA) expansion of the original sequential
circuit is referred to as circuit unrolling. In the new circuit N, after
feeding corresponding gates in C and C?to XORs, similarly to the
combinational case, it is easily seen that
?I,S?⊕ gi
The resulting PB optimization problem has the same form as (8).
Example 2 Consider the circuitˆC and the corresponding N shown
in Fig. 2. Not counting flips at FF outputs (s1), an optimal solution
to the PB optimization problem given by (8) is < S∗,I∗,I?∗>=<<
0 >,< 0,0,0 >,< 1,1,1 >>, which amounts to a total switched
capacitance of 5 units as shown in Fig. 2(a). However, this solution
might be suboptimal if gate delays are considered. Section VI
describes how delay is integrated into the PB optimization problem.
The given problem formulation allows for any initial state to be
returned in the optimal solution. Reachability analysis [20] can be
subsequently performed to verify the reachability of the solution.
SAT solvers offer a trivial way to discard unreachable solutions by
adding conflict clauses. Similarly, combinations of invalid PIs can be
eliminated using conflict clauses.
The illustrated framework can also be extended to generate peak
n-cycle power (n ≥ 1), which is the maximum average power over a
contiguous sequence of n clock cycles, by unrolling the circuit n+1
times. Each pair of corresponding gates in adjacent cycles would then
be fed to an XOR gate.
xori = gi
?I?,δ(S,I)?.
VI. MODELING DELAY
Different input signal arrival times might cause a gate to flip
several times during one clock cycle. In fact, glitches due to gate
propagation delays can often dominate the maximum instantaneous
power [7,9]. On the other hand, empirical results in [9] show that a
unit gate delay model yields reasonably accurate power estimates.
This section discusses the integration of unit gate delay into the
problem formulation. It is also explained how this can be extended
to arbitrary delay using a linear preprocessing step.
First, formal recursive definitions of max-level L(g) and min-level
l(g) are given for g ∈ G ∪ I ∪ S. L(g) and l(g) essentially denote
the lengths of, respectively, the longest and shortest simple paths to
g, in terms of number of gates, starting from a PI or a FF output.
Definition 1
?
0
L(g) =
max
{gj∈FANINS(g)}L(gj) + 1
if g ∈ G
if g ∈ I ∪ S
Definition 2
l(g) =
?
min
{gj∈FANINS(g)}l(gj) + 1
0
if g ∈ G
if g ∈ I ∪ S
Let L = maxg∈GL(g) designate the largest max-level in the
circuit. Under a unit-delay model, time t is a discrete variable,
meaningful in {0,...,L}. Moreover, the signal arrival time at the
output of gate g following a certain path from a PI or a FF output is
equal to the length of the traveled path to g.
Let Gt describe the set of all gates whose max-levels and min-
levels bound t inclusively.
Definition 3 Gt =?gi ∈ G|l(gi) ≤ t ≤ L(gi)?
Lemma 1 If every gate has a unit delay, any gate that could
potentially flip at time-step t belongs to Gt.
Proof: The contrapositive is proved. If gate g does not belong
to Gt, then either l(g) > t or L(g) < t. In the first case, the shortest
signal arrival time from an input or a pseudo-input to a fanin of g
takes at least t time-steps. So g can only flip strictly after time-step
t. Similarly, g can only flip strictly before time-step t.
Consider a circuit whose gate logic values have stabilized given
initial state S and PI vector I. If PI vector I?is applied at the start
of a new clock cycle (t = 0), then let gt(S,I,I?) denote the output
of gate g right after time-step t. Note that the output value of g
depends on both I and I?because if t < l(g), gt(S,I,I?) = g(S,I).
Accordingly, the total switched capacitance is given as follows:
L
?
The outer summation in Eq. (10) adds up the total switched
capacitances across time-steps. The inner summation adds up the
capacitances of the gates whose outputs flip at time t. Due to Lemma
1, one need not check all the gates at time-step t, but only the gates
in Gt.
The procedure to maximize the right-hand-side of Eq. (10) relies
on the construction of a new circuit N that will be used by the
PB-SAT solver. This is illustrated with the use of an example.
Consider the sequential circuitˆC shown in Fig. 2(a). First, FF inputs
(outputs) are transformed into circuit pseudo-outputs (pseudo-inputs).
Generating the sets {Gt}L
First traversal starting from PIs and pseudo-inputs. For the circuit in
Fig. 2(a), these sets are as follows:
P ∝
t=1
?
gi∈Gt
Ci
?gt−1
i
(S,I,I?) ⊕ gt
i(S,I,I?)?
(10)
t=1forˆC takes linear time using a Breadth
G1 = {a,b,d},G2 = {b,c,d},G3 = {c,d},G4 = {d}
Now, for each time-step t, for 0 ≤ t ≤ L, a time-circuit Ctis
associated, containing the following time-gates:


as shown in Fig. 3. The new circuit N (Fig. 3) accommodates all
these time-circuits {Ct}L
Next, the gate interconnections in N are discussed. The gates of
C0are interconnected identically to the original full-scanned circuit,
given pseudo-input vector S and PI vector I, as shown in Fig. 3.
For the remaining time-circuits {Ct}L
given time-gate’s fanin was originally (inˆC) i) another gate, ii)
a PI, or iii) a FF output. In case i), the given time-gate must be
connected to the most recent time-gate corresponding to the original
G(Ct) =

?gt
g0
i|gi ∈ Gt
i|gi ∈ G(ˆC)
?
if t ≥ 1
if t = 0,
?
?
(11)
t=0.
t=1, there are three cases: The

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b1
b0
b2
c2
c3
c3
a0
c2
a0
s1
d0
i1
i2
a0
a1
b1
b2
a1
i?
3
i3
i?
i?
1
2
i?
3
xor5
xor4
xor6
xor7
xor8
xor9
d2
d2
d3
d3
c2
c2
c3
C1
c0
C1= 2
C2= 1
C3= 1
C4= 1
C5= 1
C6= 1
C7= 1
C8= 1
C9= 1
d2
d4
d3
d4
a0
a1
b0
b1
b1
b2
d0
d1
d1
C4
C3
C2
N
a0
c0
xor1
C0
xor3
xor2
c0
a0
d1
c0
a0
Fig. 3. Unit-delay sequential PB-SAT formulation
fanin gate strictly before the current time-step: No two time-gates in
the same time-circuit can be connected because they can only change
simultaneously. In case ii), the given time-gate must be connected to
the corresponding new PI in I?. In case iii), the given time-gate must
be connected to the pseudo-output in C0corresponding to the FF to
which it was originally connected.
Formally, consider a gate g ∈ˆC, such that FANIN(g) = {f,i,s},
where f ∈ G(ˆC),i ∈ I(ˆC),s ∈ S(ˆC). In the new circuit N, for
each time-step t ≥ 1 where gtexists, it will be connected to the
following fanins:
?
where each fanin corresponds to one of the different cases.
It can be shown that the output every time-gate gt
consistent with its given definition in Eq. (10). In fact, the outputs of
the time-gates in C0represent the steady-state values of the original
circuitˆC given initial state S and PI vector I. This is consistent with
the given definition of g0(S,I,I?) used in Eq. (10). Furthermore, the
construction is made such that in each time-circuit, from C1to CL,
the new signals coming from the pseudo-outputs of C0and the new
PI vector I?propagate through exactly one additional gate. Therefore,
the value at the output of time-gate gtin Ctwill be equal to that of
gate g inˆC after t time-steps, which is again consistent with Eq. (10).
The final step is to add an XOR gate for every pair of originally
identical time-gates that are not separated by another identical time-
gate between their respective time-circuits, as shown in Fig. 3. The
weighted sum of these XOR gates yields:
FANIN(gt) =fmax{j|fj∈G(Cj),j<t},i?, FANIN(s)0?
i in N is
L
?
t=1
?
gi∈Gt
Ci
?gmax{j|gj∈G(Cj),j<t}
i
(S,I,I?) ⊕ gt
i(S,I,I?)?
which is in fact equivalent to Eq. (10) because even if max{j|gj∈
G(Cj),j < t} < t − 1, time-step max{j|gj∈ G(Cj),j < t} is
by definition the last time-step before t in which gate gi could have
flipped. Hence, gmax{j|gj∈G(Cj),j<t}
i
Therefore, the problem of maximizing the right-hand-side of
Eq. (10) can be formulated as a PB optimization problem of the
same form as (8).
(S,I,I?) = gt−1
i
(S,I,I?).
a
1
s1
i2
i1
d
i3
o1
ˆC
bc
Fig. 4.Unit-delay gate switching in a sequential circuit
Example 3 Consider the circuitˆC in Fig. 4 and the corresponding
N in Fig. 3. Using a unit-delay model and not counting flips at
FF outputs (s1), an optimal solution to the PB optimization problem
given by (8) is < S∗,I∗,I?∗>=<< 0 >,< 1,1,0 >,< 0,0,1 >>,
which amounts to a total switched capacitance of 6 units as shown in
Fig. 4. It is notable that both the optimal solution and the associated
circuit activity are different than those obtained for the same circuit
with the zero-delay model in Example 2.
The procedure outlined in this section can be extended to an
arbitrary delay model as follows. A linear time preprocessing step
is described in [7], which generates, for each gate, the sequence of
time instants at which it might flip. For each gate g, let ti
tf
might flip. A circuit-level time sequence that includes all possible
gate flipping time instants can be subsequently created. In order to
apply the methodology described in this section to an arbitrary delay
model, for each gate g, l(g) and L(g) should be respectively set to
the indices of ti
g and
g respectively denote the first and last time instants at which g
gand tf
gin the circuit-level time sequence.
VII. OPTIMIZATIONS AND HEURISTICS
In this section, optimization techniques to reduce the size of the
PB problem and a heuristic to guide the search are presented.
c3
b2
a0
a1
b1
b2
a1
i?
3
b1
a0
c2
a0
b0
c3
c2
C0
C3
C2
C1
N
a0
c0
xor1
xor3
xor4
xor5
xor6
xor2
C1= 2
C2= 2
C3= 2
C4= 1
C5= 1
C6= 1
C4
s1
d0
d1
c0
a0
d3
d4
a0
a1
b0
b1
b1
b2
d0
d1
d1
d3
d3
d4
i1
i2
i3
i?
i?
1
2
i?
3
Fig. 5. Optimized unit-delay sequential PB-SAT formulation
Optimization 1. The definition of the sets {Gt}L
tightened. In fact, it is sometimes known in advance that a certain
gate g will never flip at time-step t even though g ∈ Gt. This can
happen if l(g) ≤ t ≤ L(g), but there exists no path p of length
exactly t (|p| = t) from a PI or FF output to the output of g. For
example, in the circuit of Fig. 2(a), although l(d) = 1 and L(d) = 4,
d can never flip at time-step 2. Hence, in Fig. 3, the time-gate d2is
redundant because its output will always be the same as that of d1.
The following is a tighter definition of Gt.
Definition 4 Gt =?gi ∈ G|∃p : x
The sets {Gt}L
First traversal of the original circuit, starting from PIs and pseudo-
inputs and memorizing the set of newly reached gates at each time-
step. In Fig. 5, N is optimized to use Def. 4 for {Gt}L
Optimization 2. Suppose gate g is a buffer or an inverter. If the input
of g flips, then the output of g flips. Therefore, for every sequence
of buffers and/or inverters, it is sufficient to put only one XOR at the
input of the first buffer/inverter and to add the load capacitances
of the other gates to that XOR’s original weight. In Fig. 5, this
optimization is used to reduce the number of XORs. For large circuits
with significant numbers of inverters and buffers, this can significantly
reduce the size of the constructed circuit N, and therefore the number
of clauses in the CNF of the PB optimization problem.
t=1in Def. 3 can be
p
? gi,x ∈ I ∪ S,|p| = t?
t=1can be generated in linear time using a Breadth
t=1.

Page 5

Heuristic. As described in Subsection III-B, the PB-SAT solver
gradually tightens the upper bound on the objective function, and
therefore the lower bound on maximum circuit activity (8). This is
done until either the absolute maximum is found or the solver is
timed-out. However, instead of starting from an activity of 0, it is
possible to first run random simulations for R seconds, record the
generated maximum activity M and then force the solver to start
from an activity of at least α×M, for some user-specified α ∈ [0,1],
using an appropriate conflict clause. If α is close to 1, this has the
advantage of guiding the solver into parts of the search-space that
might potentially yield higher circuit activities, and saves it the time
of finding possibly many suboptimal solutions in other parts of the
search-space. However, this will make the initial SAT problem harder.
Therefore finding the first solution that yields a circuit activity greater
than α × M may take a longer time. Moreover, the PB-SAT solver
may have a harder time learning from its mistakes.
VIII. EMPIRICAL RESULTS
Both the zero-delay and unit-delay formulations of the proposed
PB-SAT based approach for circuit activity estimation are imple-
mented in C++ using MINISAT+ [17] as the underlying PB-SAT
engine. The optimizations and the heuristic described in Section VII
are also integrated. All experiments are conducted on a Pentium
IV 2.8 GHz Linux platform with 2 GB of memory. Our approach
(PB-SAT) is compared to parallel-pattern random simulations (SIM)
with 32-bit words (32 simultaneous vector simulations). Since it is
generally believed that the switching probability of the PIs of a circuit
is positively correlated to that of internal gates [6], the switching
probability of the PIs is set to 0.9 in SIM. All experiment runs,
both PB-SAT and SIM, are timed-out after 10,000 seconds, and
the generated sequence of strictly increasing activities along with
their corresponding run-times is recorded for each. Depending on
the size of the circuit, roughly 1,000,000 to 40,000,000 vectors
are simulated in 10,000 seconds for SIM. On the other hand, two
sets of PB-SAT experiments are performed, one for α = 0 and one
for α = 0.9. For α = 0.9, random simulations are first run for R = 5
seconds to extract the initial maximum activity estimate M.
Table 1 shows the experimental results for ten ISCAS85 and
twenty ISCAS89 circuits. The first and second rows respectively
show the circuit names and the corresponding numbers of gates.
The maximum circuit activities in Table 1 are in units of switched
capacitance, where Ci = |FANOUTS(gi)| for internal gates and
Ci = 1 for primary output gates. For each experiment, the generated
maximum activity values are recorded after 100, 1,000 and 10,000
seconds. For each circuit and delay model, activities are compared
between the three sets of experiments (PB-SAT,α = 0), (PB-
SAT,α = 0.9) and SIM. The higher activity after each time-period
is highlighted in bold. An empty table cell indicates that no bound
is found up to that time. A bound that remains unchanged from the
previous recorded time is highlighted in italic. Finally, a “∗” next
to an activity value indicates that the PB-SAT solver proved that
the generated activity is in fact the absolute maximum. For instance,
using a unit-delay model, in circuit s1488, (PB-SAT,α = 0) yields
the highest activity (1450) at 100 seconds, both (PB-SAT,α = 0) and
(PB-SAT,α = 0.9) prove the maximality of 1450 by 1,000 seconds,
whereas the maximum activity generated by SIM remains unchanged
(1250) after the 100 second mark.
In many circuits, the estimation improvement from simulations
is considerably large. For instance, using a unit-delay model, in
circuit s1423, (PB-SAT,α = 0) and (PB-SAT,α = 0.9) respectively
record 196% and 177% improvements over SIM. c6288 constitutes a
special case because of its disproportionately large number of levels
(L = 164), which causes N, and subsequently the CNF of the SAT
problem, to be very large.
Proving maximality is hard because it requires a virtual exam-
ination of the complete search-space. For instance, using a zero-
delay model, in circuit c880, the solver converges to an activity
of 482 before the 1,000 second mark, but only later proves its
maximality. In 53.3% of zero-delay experiments and 43.3% of unit-
delay experiments, the PB-SAT solver proves maximality. To the
best of our knowledge, this is the first work to compute the proven
maximum activities for these circuits.
For combinational circuits, our approach yields an average of
13% improvement over simulations with a zero-delay model, and
18% with a unit-delay model, comparing both methods after 10,000
seconds. For sequential circuits, our approach yields an average of
49% improvement over simulations with a zero-delay model, and
42% with a unit-delay model, comparing both methods after 10,000
seconds. The greater improvements for sequential circuits are due to
the larger and more intricate nature of the search-space.
Fig. 6 shows the sequences of strictly increasing activities gener-
ated by our methods and those generated using simulations, plotted
against execution time, for the ISCAS89 circuit s713, under both
zero-delay (Fig. 6(a)) and unit-delay (Fig. 6(b)) models. It can be
noted that SIM results, in this case and in most other circuits shown
in Table 1, tend to plateau after a while. In fact, as shown in Fig. 7,
which plots (PB-SAT,α = 0) (Fig. 7(a)) and (PB-SAT,α = 0.9)
(Fig. 7(b)) results against those of SIM, after 100 and 1,000 seconds,
a few points are still below the 45oline, but after 10,000 seconds,
in virtually all the cases, the activities generated by our approach
beat the ones generated by simulations during the same amount of
execution time.
20 40 6080100120140160180
300
320
340
360
380
400
420
440
460
480
Execution time (sec)
Circuit activity
SIM
PB−SAT, α=0
proved maximum activity

PB−SAT, α=0.9
proved maximum activity

(a) Zero-delay model
0200040006000800010000
200
400
600
800
1000
1200
1400
1600
1800
Execution time (sec)
Circuit activity
SIM
PB−SAT, α=0
PB−SAT, α=0.9
(b) Unit-delay model
Fig. 6.Activity vs. execution time for s713
500 1000
Maximum activity (SIM)
15002000 2500 30003500
500
1000
1500
2000
2500
3000
3500
4000
4500
Maximum activity (PB−SAT,α=0)
After 100s
After 1000s
After 10000s
45o line
(a) (PB-SAT,α = 0) vs. SIM
05000
Maximum activity (SIM)
1000015000
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
x 10
4
Maximum activity (PB−SAT,α=0.9)
After 100s
After 1000s
After 10000s
45o line
(b) (PB-SAT,α = 0.9) vs. SIM
Fig. 7.SIM activities vs. PB-SAT solver activities
IX. CONCLUSION
This work proposes a pseudo-boolean satisfiability based frame-
work, applicable to both combinational and sequential circuits, for
finding the input sequence that maximizes single-cycle circuit activity.
The method can also take into account multiple gate transitions
during a clock cycle. The experimental results are promising for
further research in low-power using SAT solvers, especially given
the tremendous rate of advancement in SAT solvers and PB-SAT
solvers.
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