Conference Paper

A Method for the Multi-Net Multi-Pin Routing Problem with Layer Assignment.

DOI: 10.1109/VLSI.Design.2009.30 Conference: VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009
Source: DBLP

ABSTRACT Interconnects are vital in deep sub-micron VLSI design, as they impose constraints, such as delay, congestion, crosstalk, power dissipation and others, and consume resources. These parameters affect the efforts for obtaining a feasible solution for the global routing of multiple nets. In addition, efforts are on for exploration and use of non-Manhattan routing architectures. In this work, we focus on the specific problem of multi-net multi-pin global Y -routing for custom-built design styles with several available routing layers. The problem is formulated as a minimum crossing Y -Steiner Minimal tree problem with multi-layer assignment. Experimental results are quite encouraging.

1 Bookmark
 · 
62 Views
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: In deep sub-micron regime, interconnect delays dominate VLSI circuit design. Thus, construction of cost-effective global routing trees is key to such designs. In order to reduce the interconnect delay, traditional Manhattan (M-) routing architectures are currently being replaced by the diagonal X architectures. A recent routing architecture is based on Y interconnects, involving the pervasive use of 0deg, 60deg, and 120deg oriented global and semi-global wirings. Unlike the X-routing, Y-routing Is observed to support regular routing grid, which as important for simplifying manufacturing processes and routing and design rule checking algorithms. In this paper, we propose a novel Y-routing algorithm which can solve reasonably sized problems in nominal time. The proposed method is capable of finding routing solutions for problem instances which could not be solved in reasonable time by some recently reported methods. Moreover, it can be easily extended for routing with any uniform orientation
    International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece; 01/2006
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: This paper presents the concept of flexibility-a geometric property associated with Steiner trees. Flexibility is related to the routability of the Steiner tree. We present an optimal algorithm which takes a Steiner tree and outputs a more flexible Steiner tree. Our experiments show that a net with a flexible Steiner tree increases its routability. Experiments with a global router show that congestion is improved by approximately 20%.
    Design Automation Conference, 2001. Proceedings; 02/2001
  • [Show abstract] [Hide abstract]
    ABSTRACT: We consider the problem of global routing, aiming to simultaneously minimize wire length and density through the regions. Previous global routers have attempted to achieve this goal; however, they minimized one of the two parameters as the main objective and proposed heuristics for minimizing the other parameter. We accomplish this task by introducing the concept of weighted Steiner trees. We propose an efficient and simple algorithm for obtaining a weighted (rectilinear) Steiner tree in the plane. The proposed global router at each step finds a weighted Steiner tree for a net, where weight of a region represents its “complexity”. Weights of the regions are dynamically changing. Experimental results on master slice chips and on benchmark examples from the Physical Design Workshop are included, and they verify the effectiveness of the proposed global router and its superiority over related global routers
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 01/1995; · 1.20 Impact Factor

Full-text

Download
13 Downloads
Available from
May 22, 2014