A Method for the MultiNet MultiPin Routing Problem with Layer Assignment.
ABSTRACT Interconnects are vital in deep submicron VLSI design, as they impose constraints, such as delay, congestion, crosstalk, power dissipation and others, and consume resources. These parameters affect the efforts for obtaining a feasible solution for the global routing of multiple nets. In addition, efforts are on for exploration and use of nonManhattan routing architectures. In this work, we focus on the specific problem of multinet multipin global Y routing for custombuilt design styles with several available routing layers. The problem is formulated as a minimum crossing Y Steiner Minimal tree problem with multilayer assignment. Experimental results are quite encouraging.
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Conference Paper: A heuristic method for constructing hexagonal Steiner minimal trees for routing in VLSI.
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ABSTRACT: In deep submicron regime, interconnect delays dominate VLSI circuit design. Thus, construction of costeffective global routing trees is key to such designs. In order to reduce the interconnect delay, traditional Manhattan (M) routing architectures are currently being replaced by the diagonal X architectures. A recent routing architecture is based on Y interconnects, involving the pervasive use of 0deg, 60deg, and 120deg oriented global and semiglobal wirings. Unlike the Xrouting, Yrouting Is observed to support regular routing grid, which as important for simplifying manufacturing processes and routing and design rule checking algorithms. In this paper, we propose a novel Yrouting algorithm which can solve reasonably sized problems in nominal time. The proposed method is capable of finding routing solutions for problem instances which could not be solved in reasonable time by some recently reported methods. Moreover, it can be easily extended for routing with any uniform orientationInternational Symposium on Circuits and Systems (ISCAS 2006), 2124 May 2006, Island of Kos, Greece; 01/2006  SourceAvailable from: Ryan Kastner
Conference Paper: Creating and exploiting flexibility in Steiner trees
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ABSTRACT: This paper presents the concept of flexibilitya geometric property associated with Steiner trees. Flexibility is related to the routability of the Steiner tree. We present an optimal algorithm which takes a Steiner tree and outputs a more flexible Steiner tree. Our experiments show that a net with a flexible Steiner tree increases its routability. Experiments with a global router show that congestion is improved by approximately 20%.Design Automation Conference, 2001. Proceedings; 02/2001 
Article: A weighted Steiner treebased global router with simultaneous length and density minimization
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ABSTRACT: We consider the problem of global routing, aiming to simultaneously minimize wire length and density through the regions. Previous global routers have attempted to achieve this goal; however, they minimized one of the two parameters as the main objective and proposed heuristics for minimizing the other parameter. We accomplish this task by introducing the concept of weighted Steiner trees. We propose an efficient and simple algorithm for obtaining a weighted (rectilinear) Steiner tree in the plane. The proposed global router at each step finds a weighted Steiner tree for a net, where weight of a region represents its “complexity”. Weights of the regions are dynamically changing. Experimental results on master slice chips and on benchmark examples from the Physical Design Workshop are included, and they verify the effectiveness of the proposed global router and its superiority over related global routersIEEE Transactions on ComputerAided Design of Integrated Circuits and Systems 01/1995; · 1.20 Impact Factor
Page 1
A method for the Multinet Multipin Routing Problem
with Layer Assignment
Tuhina Samanta
Bengal Engg. & Sc. University, India
t samanta@it.becs.ac.in
Hafizur Rahaman
Bengal Engg. & Sc. University, India
rahaman h@it.becs.ac.in
Prasun Ghosal
Bengal Engg. & Sc. University, India
p ghosal@it.becs.ac.in
Parthasarathi Dasgupta
Indian Institute of Management Calcutta, India
partha@iimcal.ac.in
Abstract
Interconnects are vital in deep submicron VLSI design,
as they impose constraints, such as delay, congestion, cross
talk, power dissipation and others, and consume resources.
These parameters affect the efforts for obtaining a feasible
solution for the global routing of multiple nets. In addition,
efforts are on for exploration and use of nonManhattan
routing architectures. In this work, we focus on the specific
problem of multinet multipin global Y routing for custom
builtdesignstyleswithseveralavailableroutinglayers. The
problem is formulated as a minimum crossing Y Steiner
Minimal tree problem with multilayer assignment. Experi
mental results are quite encouraging.
1Introduction
The VLSI layout problem is usually solved in a hierar
chical framework. Each stage of the hierarchy is optimized,
while the problem becomes manageable for the subsequent
stages. Global routing is a critical phase of this hierarchical
design flow, particularly, the physical design flow. It assigns
wires and vias to signal nets so as to obtain approximate in
terconnections of the pins of every net. Objectives in this
phase include chip size and wirelength minimization, even
congestion distribution, ensuring signal integrity, cost and
ease of fabrication, time to market, and so on. Global rout
ing is known to be a very difficult problem. In fact, finding
a feasible routing of a twopin net in the presence of con
gestion has been shown to be NPComplete [1].
Traditional global routing architectures are Manhattan.
With increasing dominance of interconnects, their is in
1This work is supported by grants from the Department of IT, Govt. of
India, New Delhi, Projects: SMDPII and R & D in Microelectronics
creasing research on and use of X and Y architectures.
Xrouting is now well appreciated in chip manufacturing
circle; however, the research community has been recently
investigating the Y architecture [2, 3]. This refers to wiring
with 0◦, 60◦, and 120◦oriented wires for onchip inter
connects. Several benefits of Y architectures visavis X
architectures have been elucidated in [3]. Routing of Y 
interconnects for multinet multipin nets is thus an inter
esting problem to be explored.
In this paper, we focus on the multinet global routing
over a number of wiring layers, for Y interconnects such
that the total length of all the routing trees is minimum.
Since each crossing of two edges will yield the insertion of
a via, yielding obstacles to routing, and increasing delays,
we attempt to minimize the number of crossings of the trees
as well.
The rest of the paper is organized as follows. Section 2
introduces some significant related works and the motiva
tion of our work. Section 3 describes the formulation of the
problem. Section 4 describes the proposed method of con
struction of Y routing trees with minimum edgecrossings
in a given number of layers. Section 5 describes the empir
ical observations , and Section 6 concludes the paper and
discusses its possible extensions.
2Literature survey
Global routing is a wellresearched problem. [8], [7]
and others present updated coverage of progress in global
routing. [5] and [6] focus on global routing issues for a
single net. The survey on multinet global routing [4] dis
cusses the recent global routing methods with emphasis on
performancedriven multinet routing. A recent report on
academic global routing [14] provides a brief review of
some of the best highperformance routing techniques of
recent times.
2009 22nd International Conference on VLSI Design
10639667/09 $25.00 © 2009 IEEE
DOI 10.1109/VLSI.Design.2009.30
387
Page 2
The existing global routing algorithms can be broadly
classified into the following categories:
Steiner tree construction, and 01 ILP [8]. The maze rout
ing algorithm finds a shortest path connecting two pins in
the presence of wiring blockages. A variant of the maze
routing techniques is the group of line probebased algo
rithms. It is important to note that Maze routing inherently
can consider one net at a time. Thus, an extension to multi
net domain requires nets to be considered one at a time, in
a particular order.
Mazeroutingandlineprobealgorithmsare, however, ap
plicable to only twopin nets. In practice, routing problems
consider nets with more than two pins. The wire length of a
routing tree, in such cases, is usually reduced by construct
ing a Steiner Minimal tree [7]. Traditional VLSI routing
problems use only rectilinear Steiner trees. However, re
cently, the use of wire geometries with other orientations
are quite predominant. Many of the Steiner tree construc
tion algorithms in literature focus on the optimization of a
single net, and do not consider wire congestion issues ex
plicitly. Nevertheless, these algorithms can be applied to se
rially route the nets, with the most critical nets being routed
before noncritical nets. When the edge cost is defined ac
cording to congestion, the Steiner minimum tree algorithms
may be applied directly to even out congestion while simul
taneously restraining the wire length [9].
Global routing may be formulated as a special type of
optimization problem, called a zeroone integer linear pro
gramming (01 ILP) problem. For a set of candidate rout
ing trees Ti= Ti,1, Ti,2, ... for net Ni, we use variable xi,j
to indicate if tree Ti,jis selected for net Ni.
Very recently, there has been a growing interest in the
construction of obstacle avoiding Steiner trees [16, 15].
The work reported in [19], which has fair relevance to our
work, proposes an algorithm for simultaneous escape rout
ing within a set of components on a printedcircuit boards
(PCB) that ensures minimum crossings of the nets in the
subsequent area routing phase.
The use of diagonal wires was exploited on PCB and in
tegrated circuits for more than a decade [12]. Y routing
and Y architecture for integrated circuits were introduced
through series of works of two different groups in [2]
and [3]. The work in [3] gives an indepth analysis of
Y architecture, and highlights the potential advantages of
the use of Y architectures visavis the Xarchitectures.
Algorithms for construction of Y routing trees appear in
[11, 10].
maze routing,
2.1Motivation of the work
To the best of our knowledge, not much work has been
reported in the area of multinet multipin routing, espe
cially with the use of nonManhattan interconnects. As
such, there are several unexplored issues and unanswered
questions in this area. In this work, we attempt to provide
an answer the following question:
Given a set of pins of several different nets, and a set of wiring
layers, can we obtain a global Y routing of all these nets using
these layers, such that the number of crossings of the routing trees
of the different nets is as small as possible?
The following Section formulates the problem, and in
troduces the basic framework for the proposed method.
3 Problem formulation
In global routing, a signal net consisting of a set of
fixed terminals Ni= {ni,0, ni,1, ..., ni,ki} is connected
by a routing tree T(Ni). The cost of the tree T(Ni) is the
sum of costs of its constituent edges. Thus, the total cost
χ(T(Ni)) of a tree T(Ni) of kinodes is given by χ(T(Ni))
= Σp
tree T(Ni). In the multinet multipin global routing prob
lem, we consider a number κ, say, of signal nets, each net
containing a number of pins = 2 to ki.
In this case, we consider a fixed set of wiring layers Λ,
say, for the placement of the routing trees, such that each
layer can have at least one Steiner Minimum Tree (SMT)
assigned to it. In order to ensure minimum routing resource
consumption, the total length of the routing trees is to be
minimum. The SMTs considered are Y routing trees.
The Minimum length minimum edgecrossing Multinet
Multipin global routing (MNMP) problem can be formu
lated as follows:
Given a number κ, say, of multipin nets Πj, j = 1 to κ,
a set of wiring layers Λ, and an upperbound on the layout
area, construct a Y routed Steiner Minimum Tree for every
net Πj, and assign the trees appropriately to the given layers
such that (i) the total length of the trees is minimum, and
(ii) total number of edge crossings of the Steiner trees is as
small as possible.
j=1t(ej), where t(ej) is the cost of edge ejin routing
4 Proposed method
In this paper, our approach broadly comprises the fol
lowing steps:
• For every net, construct the Convex Hull of its con
stituent terminals.
• Construct a matrix, each element of which contains the
amount of overlapping regions of a pair of nets. Sort
the nets in decreasing order of their total amount of
overlaps with other nets.
• Assign the minimum overlapping nets to the given set
of wiring layers in an increasing order of the amount
of overlap.
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Page 3
• If the number of wiring layers required is more than
the available number of layers, redistribute the excess
nets appropriately among the available wiring layers.
• Construct the Y routed SMTs and modify them us
ing a set of operators to minimize the number of edge
crossings between all pairs of trees in every layer.
Let Ti, Tj respectively represent the Steiner Minimal
Trees of the ithand jthnets, and CHi, CHjbe the cor
responding convex hulls. Then, the following observations
are clear.
Observation 1 Overlapping of CHi and CHj does not
necessarily imply crossing of an edge of Tiwith an edge
of Tj.
Observation 2 If CHiand CHjdo not overlap, then there
cannot be any crossing of edges of Tiand Tj.
Fromthesetofpinsforalltheκnets, findthecoordinates
of the leftmostbottommost pin position, and the rightmost
topmost pin position. Let (xmin,ymin) and (xmax,ymax)
respectively denote these coordinates. Then, the available
routing area is bounded by a rectangular box within these
set of coordinates.
We discuss the above steps below. However, the com
plete details could not be provided due to paucity of space.
4.1Convex Hull creation
Consider a given net to be a set of points in a plane,
where each point corresponds to a terminal of the net. A
convex hull CHj, j = 1 to κ is generated for each net Πj
(i.e., its associated points) using Graham’s scan algorithm
[17]. If Qjis the number of points lying over the boundary
of CHj, then 1 ≤ Qj ≤ pj, where pjis total number of
pins for the net Πj.
Definition 1 Two convex hulls CHiand CHjare said to
overlap with each other if and only if a vertex on the bound
ary of one convex hull is bounded by the other convex hull.
4.2Layer assignment of nets
Oncetheconvexhullshavebeenconstructed, theamount
of overlap of?κ
Observation 3 Intersection of a pair of convex hulls form
a convex polygon.
2
?possible pairs is obtained. Since a convex
hull is a convex polygon, the following observation is clear.
Thus, the amount of overlapping regions of a pair of convex
hulls is obtained from the area of the polygon formed by
their intersection. Figure 1 illustrates a pair of intersecting
convex hulls with a convex polygon (a,b,c,d) created by
their intersection. The circular nodes are the terminals, and
the rectangular nodes are intersections of the boundaries of
the convex hulls.
a
b
c
d
Figure 1. Overlapping Convex Hulls
Next, the convex hulls are arranged on the number of
vertices along their boundaries, and are assigned to the lay
ers in that order. Consider the layer numbers to be 1 to  Λ 
from bottom to top. The largest (in terms of the number
of vertices along boundary) convex hull is the first to be as
signed to layer 1. Next, the set of convex hulls, if any, which
do not intersect this initially assigned convex hull, and are
mutually nonintersecting with each other, are assigned to
layer 1. Once the assignment to layer 1 is complete, layer
2 is the next to be considered. The same procedure is ap
plied to layer 2 as well. The iterative assignment completes
when either (i) all the nets have been considered, or (ii) all
the layers have been considered, and some nets are yet to
be assigned. In the second case, when some nets are yet to
be assigned, for each of the leftover net, its most potential
layer assignment is determined by finding the total overlap
ping area of this net with the already assigned nets for every
layer.
Definition 2 A wiringlayer Λj is considered to be most poten
tial for assignment of a net Πi if the total amount of overlap of
the convex hull of net Πiwith the convex hulls of the nets already
assigned to Λj is minimum among all the layers.
For a net Πi, once its most potential layer is determined, Πi
is assigned to this layer.
4.3Construction
Minimum Tree
of
Y RoutingSteiner
The Y Routing Steiner Minimum Tree is constructed us
ing a heuristic method. The proposed method depends on
the computation of shortest paths between pairs of nodes in
an underlying Hanan grid graph. Initially, a pair of termi
nals in the given problem that are farthest apart in Euclidean
space, is obtained. It attempts to find the shortest path be
tween these terminals in the underlying routing graph. An
iterative sequence of steps is executed thereafter. At each
iteration, the following steps are executed in sequence:
1. A partial SMT denoted by Gpartial, is constructed.
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2. For each of the remaining terminals, find the Euclidean
distance of the terminal from its nearest Steiner node
in Gpartial.
3. Find the maximum of all the Euclidean distances ob
tained in the previous Step. Let p be the corresponding
terminal, and q be the corresponding Steiner node in
Gpartial.
4. Find the shortest path between p and q in the underly
ing routing graph; augment Gpartialwith this shortest
path.
The iteration stops when all the terminals have been consid
ered, and Gpartialis reported as the Y routing Steiner tree.
Figure 2 illustrates a partially grown Y routing tree in an
underlying Hanan grid for a net.
a
e
c
d
b
a
c
d
b
f g h
Figure 2. Example of YRouting SMT
We refer the readers to [10] for the details of the algo
rithm.
4.4 Transforming Steiner trees
Once the Steiner trees are constructed in the different
layers, the pairs of Steiner trees with intersecting edges are
identified. A set of operators [18] are applied on these
Steiner trees for possible transformation to a different set
of Steiner trees, such that the number of intersections is re
duced. We apply the following set of operators:
• Operator M1: Flipping an edge of the Steiner tree (see
Figure 3).
• Operator M2 : Inserting detours (see Figure 4).
• Operator M3 Sliding an edge of the Steiner tree com
prising two Steiner vertices.
• Operator M4: Moving a single Steiner node along an
edge (see Figure 5).
M1
Figure 3. Application of operator M1
M2
Figure 4. Application of operator M2
Net1
Net2
M4
Net1
Net2
Figure 5. Application of operator M4
In Figures 3, 4 and 5, the figures on left and right re
spectively illustrate Steiner Minimal Trees before and after
application of the operators. Consider Figures 3 and 4. The
dashed lines illustrate the respective edges that are removed
after application of the operators ”edge flip”, and ”detour”.
Detailed explanation of all the operators could not be given
due to paucity of space.
4.5 The algorithm
The overall algorithm for solving the MNMP problem
for a fixed number of layers is as described in Figure 6.
4.6Time complexity
As mentioned above, let κ be the total number of nets,
and Nibe the number of pins in ithnet, where i = 1 to
κ. The number of layers is denoted by  Λ . Let N =
total number of pins for all the nets. Then worstcase time
complexity of the proposed algorithm (Figure 6) is given by
Lemma 1.
Lemma 1 The time complexity of MNMP is O( Λ 
×κ2) + O(κ × N3logN), where N is the total number
of pins (terminals) of all the nets.
Proof. The proposed algorithm (Figure 6) is divided into
a number of phases. Time complexity of constructing the
convex hull of the ithnet using Graham’s scan is O( Ni
log  Ni ), where Niis the set of pins/terminals of the
ithnet. Time complexity of finding the amount of overlap
of convex hulls for a pair of nets, say, ithand jthnets, is
O(( Ni +  Nj )log( Ni +  Nj ) + klog( Ni
390
Page 5
Algorithm for the MNMP problem
Input: a set of terminals P for a number of nets;A set Λ of wiring layers
Output: Minimumintersecting Y −routed Steiner Minimal Trees for
the nets assigned to Λ.
1. layout area = compute layout area()
(* compute the layout area from the pin coordinates *)
2. (* Convex hull construction for nets *)
3. for i = 1 to κ Ci= Generate Convex Hull(Πi)
4. for i = 1 to κ  1
5. for j = i + 1 to κ
6.Find CH Intersect(Ci, Cj)
(* Generate a matrix of overlaps for all pairs of nets *)
7. Sort the Convex Hulls (Ci, i = 1 to κ) in
descending order of their number of vertices
8. (* assigning convex hulls to the layers *)
9. l = 1 (* layer index *)
10. c = 1 (* index of convex hull / net *)
11. while (not all nets assigned) and (not all layers considered) do
12. assign convex hull CHcto layer l
13.
Areal= area of CHc; (* initialize consumed area *)
14.while (∃ net p not intersecting any of the nets assigned
to layer l) and (p is not already assigned)
15. if temparea l (= Areal+ area of CHp) ≤ layout area
16.assign net p to layer l; Areal= Areal+ area of CHp
17.
l = l + 1
18. if (all nets assigned) and (not all layers considered)
19.Total number of layers = l; return
20. if (not all nets assigned) and (all layers considered)
21. (* distribute the remaining nets over the layers *)
22. for each remaining convex hull CHc
23. find the most potential layer lmin(* min overlap *)
24. assign CHcto lmin
25. Generate MST();(* construct the Y routing trees *)
26. for l = 1 to total number of layers
27.transform MSTs in layer l to minimize their mutual intersections
Figure 6. Algorithm for the MNMP problem
+  Nj)), where k = number of vertices of the polygon of
intersection [17]. Then, the total time complexity for all the
?κ
hence O(N2logN). Time complexity of sorting the nets
in decreasing order of the number of constituent vertices is
O(κlogκ).
Assigning nonoverlapping nets to  Λ  layers re
quires checking one net per layer against all the other nets.
Since we store the information on overlapping nets in a 2
dimensionalsymmetricmatrix, thenthetimecomplexityfor
this part is O( Λ  ×κ2). In the worstcase, this should also
be the time complexity of finding the most potential layer
for a net.
Time complexity of constructing a Y routed Steiner
Minimal Tree for the ithnet is O(N3
time complexity for constructing Steiner trees for all the
nets is then O(κ × N3logN). Finally, the worstcase time
complexity of applying transformation operators on all the
Steiner trees is O(N3).
Thus, the overall worstcase time complexity of the
proposed algorithm for the MNMP problem is roughly
O(N2logN) + O( Λ  ×κ2) + O(κ × N3logN) + O(N3)
+ O(κlogκ) ? O( Λ  ×κ2) + O(κ×N3logN), for large N.
2
?pairs of convex hulls is Σκ−1
i=1Σκ
j=i+1( Ni +  Nj 
)log( Ni +  Nj)+klog( Ni +  Nj) ≤ N2logN,
ilogNi) [10]. Total
5 Experimental Results
The proposed algorithm is implemented in C on a PIV
machine at 2.5 GHz running on Linux. A set of benchmark
instances available at [20] are used as inputs for the pro
posed algorithm. For construction of the grids, and com
putation of the layout area on each layer, we consider the
technology node parameters for 65nm from [21]. The grid
granularity is varied from bottom to top layers as per con
vention. The outcomes of the experiments are summarized
in Table 1. Area shown in the table is in grid units for 65nm.
The results indicate that our method can handle larger num
ber of nets compared to [19] in much less CPU time. Figure
7, for a particular number of layers, confirms our expression
of time complexity as a function of the number of nets. Fig
ure 8 illustrates bar charts for different problem instances
showing the overlap counts of nets before and after layer
assignment.
CPU execution time
0
500
1000
1500
2000
2500
3000
3500
5001000 15002000250030003500
no. of nets
executin time (sec)
Figure 7. CPU time vs. Number of nets
0
10000
20000
30000
40000
50000
60000
70000
123456
Problem Instance
Overlap count
Total overlapped nets
Overlap  L1
Overlap  L2
Overlap  L3
Figure 8. Overlap reductions of nets
6 Conclusion and Future Scope
In this work, we consider the problem layer assignment
of multipin multinets with minimum edge crossings.
The proposed algorithm and the observations are very
useful for the following reasons: (i) the MNMP problem
is of immense importance in VLSI physical design flow,
(ii) the proposed algorithm is comprehensive, handles some
critical issues related to multinet routing, and handles a
large number of nets in reasonable CPU time, (iii) to the
best of our knowledge, not much has been reported in liter
ature so far on this problem, and (iv) the MNMP problem
391
Page 6
Problem
instance
bench1
# of
nets
1557
Layout
area
120395000.0
# of layers
used
3
CPU time
(secs.)
730.01
Layer details
# nets placed
1360
184
13
811
241
605
19
1579
1112
3014
257
1244
148
584
72
38
2814
159
layer #
1
2
3
1
2
3
4
1
2
1
2
1
2
3
4
5
1
2
Area used
120394997.5
120394218.5
16723865.0
121682960.5
121682958.5
121649628.5
107261782.5
121109999.0
77015672.5
121010991.0
55570606.0
119289977.0
119289980.5
119289980.5
119125470.5
173328775.0
120758111.5
13179302.0
bench21676121682961.04824.39
bench32691 121110000.02 2782
bench43271121010998.022954
bench52086119289984.051349.14
bench62973 120758121.022509.16
Table 1. Summary of results for some ISPD2007 benchmark instances (adaptec1.capo70.2d.35.50.90)
for Y interconnects does not seem to have been tackled in
the existing literature.
Thepresentworkhaswidescopeof extension: (i)further
minimization of crossings of the Steiner trees, (ii) certainly,
the consideration of vias between layers with via minimiza
tion. Studying the variation of the extent of SMT edge
crossing minimization with order of the net assignments
would be another interesting extension.
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 Available from Prasun Ghosal · May 22, 2014Available from 10.1109/VLSI.Design.2009.30