ETAM++: Extended Transition Activity Measure for Low Power Address Bus Designs.
ABSTRACT Interconnection networks in SystemsOnChip begin to have a nonnegligible impact on the power consumption of a whole system. This is because of increasing interwire capacitances that are in the same order of magnitude as intrinsic capacitances as far as deepsubmicron designs are concerned. This trend has been recognized in recent research work. In this work, we present a physical model that takes into account interwire capacitances. Subsequently we propose a novel encoding scheme based on this physical model and targeted for address buses. We demonstrate that our encoding method improves power consumption by up to 62.5% and thus is exceeding all current approaches including our own previous one. In addition, the hardware of the bus encoding/decoding interfaces is compact to implement. We have conducted extensive simulations using SOC applications like, for example, an MPEGII encoder to evaluate the advantages of our approach.
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ABSTRACT: SystemsonChip (SoC) design involves several challenges, stemming from the extreme miniaturization of the physical features and from the large number of devices and wires on a chip. Since most SoCs are used within embedded systems, specific concerns are increasingly related to correct, reliable, and robust operation. We believe that in the future most SoCs will be assembled by using largescale macrocells and interconnected by means of onchip networks. We examine some physical properties of onchip interconnect busses, with the goal of achieving fast, reliable, and lowenergy communication. These objectives are reached by dynamically scaling down the voltage swing, while ensuring data integrityin spite of the decreased signal to noise ratioby means of encoding and retransmission schemes. In particular, we describe a closedloop voltage swing controller that samples the error retransmission rate to determine the operational voltage swing. We present a control policy which achieves our goals with minimal complexity; such simplicity is demonstrated by implementing the policy in a synthesizable controller. Such a controller is an embodiment of a selfcalibrating circuit that compensates for significant manufacturing parameter deviations and environmental variations. Experimental results show that energy savings amount up to 42%, while at the same time meeting performance requirements.IEEE Transactions on Very Large Scale Integration (VLSI) Systems 02/2005; · 1.22 Impact Factor  SourceAvailable from: Tughrul Arslan[Show abstract] [Hide abstract]
ABSTRACT: Not AvailableIEE Proceedings  Circuits Devices and Systems 05/2006; 153(2):159 166. · 0.36 Impact Factor  SourceAvailable from: PoTsang Huang
Conference Paper: Low power encoding schemes for runtime onchip bus
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ABSTRACT: Not AvailableCircuits and Systems, 2004. Proceedings. The 2004 IEEE AsiaPacific Conference on; 01/2005
Page 1
1
ETAM++: Extended Transition Activity Measure for Low Power Address Bus Designs
Haris Lekatsas and Jörg Henkel
NEC USA
{lekatsas, henkel}@neclab.com
Abstract
Interconnection networks in SystemsOnChip begin to
have a nonnegligible impact on the power consumption of
a whole system. This is because of increasing interwire
capacitances that are in the same order of magnitude as
intrinsic capacitances as far as deepsubmicron designs
are concerned. This trend has been recognized in recent
research work. In this work, we present a physical model
that takes into account interwire capacitances.
Subsequently we propose a novel encoding scheme based
on this physical model and targeted for address buses. We
demonstrate that our encoding method improves power
consumption by up to 62.5% and thus is exceeding all
current approaches including our own previous one. In
addition, the hardware of the bus encoding/decoding
interfaces is compact to implement. We have conducted
extensive simulations using SOC applications like, for
example, an MPEGII encoder to evaluate the advantages of
our approach.
1. Introduction
With the advent of SystemsonChip (SOC) that will reach
1 billion transistors within the next couple of years, the
complexity and the physical length of bus
systems/hierarchies will lead to an increased contribution to
a chip’s total power consumption. And most importantly,
the closer geometrical proximity of adjacent bus lines will
lead to effects that are almost negligible in technologies not
advanced as 0.1micron and beyond. This is because two or
more close bus lines will form a parasitic capacitance
between them. This effect not only leads to crosstalk and
delay effects it also leads to an increased power
consumption since the parasitic capacitance is charged and
discharged when there is a voltage swing between two or
more bus lines. This effect takes place in addition to the
intrinsic capacitance of a bus line i.e. the parasitic
capacitance between the bus line and various metal layers
beneath. Hence, more energy is being consumed.
There are several ways to diminish or at least reduce the
problem of interwire capacitances. One way is to widen
the distance between bus lines. However, this is typically
not preferred since the total area of the bus systems grows
too large. Another option is to use P&R tools (place &
route) that avoid sidebyside routing of bus lines. This is
what is actually done in the newest generation of P&R
tools. However, the interconnect complexity of a 1billion
transistor SOCs with multiple bus hierarchies and long
buses with many cores connected to them will prevent a
satisfying solution at a feasible routing time (complexity of
the routing problem). A third option is to change the
geometrical shape of bus lines: the bus lines themselves can
be reshaped. For example the crosssectional shape can be
made narrower such that the distance between two bus lines
increases without sacrificing space for the whole bus.
However, the main disadvantage of this approach is that the
crosssectional area of a bus line is fixed since the current
perarea ratio is fixed for any certain technology. That
typically leads to solutions where the bus line is buried
deeper into the substrate with the height being larger than
the width of a bus line. However, even though the inter
wire capacitance decreases due to a decreasing distance
between bus lines, it does increase due the increased flank
area of two opposing bus lines. In conclusion: what is won
through a wider distance has to be, at least partly, given up
through the effect of larger flank area.
Finally, another technique to reduce power due to inter
wire capacitances is through the use of bus encoding
techniques. In our research we focus on such a technique,
namely on finding an energyefficient bus encoding
technique. The reason is that a bus encoding technique can
be applied in addition to other techniques discussed above.
We will furthermore show that our approach delivers
higher energy savings than any other bus encoding
technique proposed so far. Before presenting our encoding
method, we will discuss in detail the physical model that
forms the basis of our approach. Unlike most previous
work for bus encoding, we take into consideration both the
intrinsic and the interwire capacitances and present a
model that is more accurate compared to our previous work
[16]. Our work focuses on address buses and the proposed
encoding scheme takes advantage of the special
characteristics of address bus transactions. However, no a
priori knowledge of the application is necessary. We have
conducted extensive experiments and found high energy
savings across different application domains.
This paper is structured as follows: Section 2 discusses
related work in the area. Section 3 provides an introduction
to our techniques and describes our previous method as
discussed elsewhere [16]. Section 4 proposes the new
physical model estimating the power consumption of bus
lines and taking into accounts coupling (i.e. interwire)
effects. Section 5 describes our ETAM++ scheme, which is
used to selectively invert words transmitted on the address
bus. Section 6 presents experimental results, while Section
7 concludes.
Page 2
2
2. Related Work
In recent research the abovementioned trend of the
increasing importance of interconnect in terms of power
consumption has been recognized. In the following we will
discuss basically two groups of related work: first, work
that tries to minimize the number of transitions on buses to
reduce power assuming that interwire capacitances are
negligible and secondly a group of work that assumes that
interwire capacitances do matter. The latter group applies
to the newest technologies and thus is most relevant to our
work.
Early work on minimizing the transition activities on buses
has been conducted by Stan/Burleson [11]. The idea is to
transmit the inverted word through the bus when the
Hamming Distance (HD for simplicity) of the noninverted
word would result in HD > N/2 with N being the number of
bus lines. This requires minimal additional logic only, plus
one control bus line that tells whether invert mode is being
applied for a particular transition or not. Panda/Dutt [7]
approached the problem of reducing switching activities of
address busses by exploiting the characteristics of accesses
to memory arrays. They investigated various scenarios for
memory mapping schemes due to different memory
organizations.
Benini et al. [2] present an adaptive approach for encoding
signals that are transmitted through wide and heavily
loaded buses. The exploitation of correlated access patterns
(like in address buses) has been studied in (see above) by
using Gray Code encoding according to Metha et al. [6]
and Su et al. [14]. Benini et al. [3] have improved upon
Gray Code through their method called T0 that benefits
from the fact that a fairly high number of patterns in
address buses are consecutive. Then, the receiving side of
an address bus can calculate the address without the
necessity to actually having the address code being
transmitted via the address bus. Working Zone Encoding
has been proposed by Musoll et al. [6]. They perform
encoding adjusted to where on an address word switching
activity actually takes place. A synthesis method for a
spatially adaptive bus interface is presented by
Acquaviva/Scarsi [1] that does not need any a priori
knowledge of the data being transferred. Ramprasad et al.
[8] present a framework to study various encoding schemes
for address and data buses that can be applied to high
capacitance buses. The approach of Zhang et al. [15], is to
segment a bus and thus exploit the effect of having smaller
effective bus capacitances applying during bus transitions.
Another systemlevel oriented approach for communication
architectures is presented by Stan/Burleson [12] as they
focus on low power encoding techniques under specific
consideration of influences on possible area and
performance impacts.
The following work consists of the most recent approaches
that take interwire capacitances into consideration.
Sotiriadis/Chandrakasan [10] use a static encoding
technique (i.e. an encoding technique that is fixed) and
obtain results of an average of 40% power savings. Another
approach is introduced by Kim et al. [4] where a coupling
sensitive invert scheme is introduced leading to around
30% power savings. The work of Shin/Sakurai [9] presents
a coupling driven bus encoder that capitalizes on the fact
that the data sent via the bus might be known a priori. They
report for those cases up to 46% energy savings. Taylor et
al. [13] present an approach to model the power
consumption of interconnects.
We can summarize the related work with respect to our
work as follows: there have been many approaches to bus
transition reduction resulting in significant reduction in bus
power consumption. However, reducing transition activity
i.e. the number of low/high, high/low transitions is not
necessarily leading to low power consumption in deep sub
micron designs as we will show throughout the course of
this paper. Deep submicron characteristics of buses and
the exploitation of these effects are just starting to be taken
into consideration, since designs with those characteristics
interwire capacitances are in the same order of magnitude
as intrinsic capacitances are to be launched in the not so far
future. As opposed to other approaches (see above) taking
this effect into consideration, our approach has additional
features: our coding scheme is adaptive and thus it can
exploit characteristics on the (address) bus that are
changing over time. As opposed to [10] we do not assume
any a priori knowledge of the application running on the
system. Furthermore, we are able to improve power
consumption by up to 62.5%.
3. Assumptions and Previous Work
The work presented in this paper presents a major
improvement over our previous work. In this paper we
present a new technique that is used as the basis for a low
energyconsumption Bus Encoding Interface (BEI). For a
proper understanding of this paper the knowledge and
principle of our previous work is crucial and therefore the
main ideas are summarized here.
The following assumptions/observations hold:
A. In deepsubmicron designs of 0.1u and beyond
there are interwire capacitances i.e. capacitances
between bus lines that will consume energy when
transitioning from
capacitances are in the same order of magnitude
than intrinsic capacitances i.e. the capacitances
between single bus lines and the various metal
layers [16].
B. Since there are capacitances between wires (and
not only between adjacent wires but also, at least
to a smaller degree, between a wire ‘A’ and a wire
‘C’ with a wire ‘B’ in between, for example) every
wire has a different effective capacitance to
switch: those wires with no or less adjacent wires
have a smaller capacitance to switch; those wires
with two or more adjacent wires have a higher
capacitance to switch. This leads to a different
energy consumption depending on where (i.e.
which bus line) the information is being
transferred. This work concentrates on buses. One
of the most important characteristics of address
buses, as far as this work is concerned, is the fact
that lower bits tend to switch more often than
0>1 or 1>0. These
Page 3
3
higher bits. Thus, the profile of an address bus has
similarities with a counter. In our previous work
we exploited this effect via a scheme we call
ACCS. In the work presented here, we apply our
bus encoding method on top of ACCS i.e.
temporally after ACCS has been applied.
Figure 1 shows the whole bus encoding scheme. On the left
side the addresses to be encoded enter the BEI. Address
bits are reshuffled via the ACCS scheme such that bus
lines with a lesser amount of transitions (according to
assumption/observation B from above) are transmitted
through bus lines with a lower effective capacitance.
Then we apply an encoding of the incoming address words.
The most crucial part is to find a measure that can, onthe
fly, predict what is the least energy consuming encoding.
That is what we call ETAM++ i.e. Extended Transition
Activity Measure. It is a measure that does not only count
the number of transitions but that also accounts for the
interwire effects. ETAM++ will then control the invert
encoder that actually does the selective encoding.
The work presented here focuses on ETAM++ since it is
the heart of our scheme that makes the highenergy savings
of our bus encoding interface possible. The next section
will explain and derive the ETAM++ scheme in detail.
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????????
?????? ?????????
??????? ???????
?
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??????? ??? ?????????????
??????? ??? ?????????
Figure 1: Bus encoding interface (BEI)
4. Interwire Capacitance Model
In this section we describe the physical model we use to
calculate power consumption due to interwire (i.e. cross
coupling) capacitances. This leads us to what we call the
ETAM++ definition. We will show how to use ETAM++ to
minimize power consumption by selectively inverting the
words transmitted on the address bus.
In Figure 2 two bus lines, i and j, are shown. CB is the
intrinsic capacitance (base capacitance) between each bus
line and the ground (i.e. underlying metal layers) and Cij is
the coupling capacitance between these two bus lines i and
j. Note that these bus lines are not necessarily spatially next
to each other (though we have found that those who are
spatially next to each other have the largest coupling
capacitances between them). Ei is the voltage applied to the
bitline and can either be equal to VDD or 0, depending on the
logical value that is transmitted via the bus. The R’s are
resistances on which energy is dissipated. We will now
derive the power consumed during bit transitions based on
this model. It is the first step towards deriving the
ETAM++ scheme.
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Figure 2: Model diagram
We will derive the scheme for what we call a window. A
window in our definition is a contiguous series of bits (bus
lines) on the bus. The reason is that within one window
interwire capacitances do have an impact whereas inter
wire capacitances between bus lines of a certain window
and a bus lines outside of that window is negligible. We
have found (not shown here) that four bits for a window are
an adequate size as a compromise between the effort for
deriving the ETAM++ scheme on the one side and the
amount of the interwire effects on the other side. Note that
the whole bus is partitioned into such 4bit windows and to
each of these windows the ETAM++ scheme is applied.
Assume that the bit values in our 4bit window are B0, B1,
B2, and B3 respectively. In the previous cycle (temporally
preceding) the corresponding values were B0
B3
constant during the transition period and take the value
dictated by Bi. Assuming the voltages on the bus lines are
Vi(t) as shown in Fig. 1, the following equations hold:
Ei =VDD*Bi (1) Vi(0)=VDD*Bi
Vi(∞)=VDD*Bi
Equation (1) shows that for any t>0 Ei is either zero or
equal to VDD, depending on the new value of bit Bi.
Equation (2) shows that the voltage Vi of each bus line i is
initially, i.e. at time t=0, equal to the previous bit value B0
Finally Equation (3) shows that at time t=∞ we assume that
voltage Vi settles down to the value of Ei.
By applying Kirchhoff’s law, we find that all bus line
voltages Vi(t) satisfy the following differential equations:
1, B1
1, B2
1, and
1 respectively. The voltages Ei are assumed to remain
1
(2)
(3)
1.
Equation (4) shows current inflow equilibrium in node i
(Kirchhoff’s law).
Let
(4)
dt
j
V
i
V
(
d
ij
ij
C
dt
i
dV
B
C
R
i
V
i
E
)
−
∑
≠
+=
−
(7)Cij *R
=
Tij (6), CCC (5), CC
iB
ii
ij
iji
+−==∑
≠
)(
Page 4
4
Note that the negative sign in Eq. (6) for Cii has no physical
meaning. We define as a mathematical tool to simplify our
final results. Also note that matrix Tij is symmetric i.e. Tij =
Tji. Using Eq. (5), (6), (7) and (4) we derive:
Power is proportional to the square of voltage, thus Eq. (8)
can be rewritten as:
−
∑
Taking into account that all Ej’s are constant and summing
over all bus lines, we obtain the equation giving the power
dissipated on all resistances R:
∑ ∑ ∑
We integrate equation (10) to obtain the total energy
dissipated:
Integrating by parts the integral in Eq. (11)
and taking into account conditions (1) and (3), we obtain
the following result:
Using Eq. (13) and the fact that matrix Tij is symmetric it is
very simple to prove that:
1
P
ii
ij
Using equations (1) and (2) as well as (9) we obtain the
following final result:
Equation (15) calculates total power P dissipated during the
transition period. As expected P is a function of Bi and Bi
Note that this equation does not depend on the window
size. In the following we will analyze the 4bit window
case, for which our experiments exhibit the best results in
terms of power reduction.
5. ETAM++ Scheme
In this section we will specialize the general physical
power model presented above for a 4bit window (i.e four
adjacent bus lines). As mentioned above our simulations
have shown that partitioning a 32bit bus into 8 subgroups
where each subgroup is a 4bit window is advantageous. A
discussion of this is beyond the scope of this paper, and the
reader should refer to [16] for more information.
In the 4bit window (we will just use ‘window’ in the
following for brevity) lets look at the capacitance from the
point of view of one of the four bit lines. Assume CB is the
intrinsic capacitance while CA,CC, and CD are the
capacitances between this bus line and its three neighbors.
Using the definitions of equations (5) and (6) from above
we can define the capacitance matrix Cij as follows:
CCCCC
ADCAB
++−
=
(
1.
In order to simplify our power scheme we make the
assumption that all coupling capacitances are of the same
order of magnitude (this is justified by physical sizes of the
actual capacitances we derived through simulation; see
[16]). We thus assume that CA = CB = CC = CD = C. Using
equations (15) and (16) we obtain:
CCCC
−
=
*4
and
(8)
dt
j
dV
j
ij
T
i
V
i
E
dt
j
dV
j
ij
C 
dt
j
dV
ij
ij
C
dt
i
dV
ii
C
R
i
V
i
E
∑
=−
⇒
∑
=
∑
≠
−−=
−
(9)
dt
dV
VET
R
1
R
VE
j
ii
j
ij
ii
)(
)(
2
−=
(10)
dt
VEd
VET
R
1
R
VE
i
jj
ii
j
ij
i
ii
−
−−=
−
)(
)(
)(
2
(11) dt
dt
VEd
VET
R
1

=
dt
R
VE
P
i
jj
ii
j
ij
i
ii
∑
∫
0
∑∑∫
∞∞
−
−
−
=
0
2
)(
)(
)(
(12) dt
dt
VEd
VE
)V(E* )V
i
(E dt
dt
VEd
VE
ii
jj
jji
jj
ii

0]
∫
0
∫
0
∞
∞
−
−
=
−
−
∞
)(
)(
)(
)(
(14) (0))}V (E*(0))V {(ET
R*2
jjij
∑∑
=
(15) )}B(B* )B
i
{(BC
2
V
P
1 
jj
1 
i
ij
ij
2
DD∑∑
−=
[ ]
C
ij
(16)
)
CCCC
(
CCC
CCCCCC
CCCCC
(
C
CC
DCABACD
A
+
CABAC
CACABA
DC
++−
++−
+++−
)* 2
)* 2
)(
[ ]
Cij
(18)
CCCC
C
*4
CCC
CCCC
−
−
−
*4
*4
(19)
}
)
BBBBBBBB
BBBBBBBBBB
BBB
−
BBBBB
−
BBBBBB
V
2
−
C
P
DD
{
( * )( *2)( * )( *2
) ( * )( *2)( * )( *2)(
* )( *2)( * )( *2)( *4
)( *4)( *4)( *4
*
1
33
1
22
1
33
1
11
1
22
1
11
1
33
1
00
1
22
1
00
1
11
1
00
21
33
21
22
21
11
21
00
2
−−−−
−−−−−
−−−−
−−−
−−−−−−
−−−−−
−−−−−
+−+−+−=
(13) dt
dt
VEd
VE 
(0))V(E*(0))V
i
(E dt
dt
VEd
VE
ii
jj
jji
jj
ii

∫
0
∫
0
∞
∞
−
−
−=
−
−
)(
)(
)(
)(
Page 5
5
Equation (19) can be transformed to:
We shall use the following definitions and identities:
−=⊕=
−
1
()[(
where
The meaning of ri and dij is:
•
ri is 1 iff there is a change of bit i. It does not contain
any information concerning the direction of the
change (0 to 1 or 1 to 0).
•
dij is 1 iff both bits, i and j, change but in the opposite
direction. In such a case the voltage difference across
the coupling capacitance is double and when squared
it results in power 4 times as high compared with the
other case described in next bullet. This explains
factor 4 appearing in eq. 22.
•
ri⊕rj, appearing in eq.(22) is 1 iff only one of the two
bits is changing. Note that if both bits are changing in
the same direction then the voltage difference across
the coupling capacitance is zero.
Using the above definitions we obtain the following:
Apart from VDD and C, all symbols appearing in the above
equation are functions of the four input bits Bi and their
previous values Bi
of the power dissipated as follows:
{
03210
⊕++++=++
1. We can therefore introduce a measure
Note that ETAM++ is used as a scheme to measure power
in a way that is easy to implement within a small logic
(otherwise the power savings we are looking for on the bus
would be eaten up by this additional logic). This logic is
implemented for each window and it decides whether
inverting the address data on the bus in beneficial in terms
of power consumption or not. Note that our definition of
ETAM++ in this paper is quite different than the scheme
presented in our previous work [16] as it is based on a
different (more accurate and easier to implement) physical
bus model. As will become evident in the experimental
section this new model yields significantly better results.
The ETAM++ takes the following values:
1. If no bit changes, i.e. ri=0 ∀i, then ETAM++ =0
2. If only one bit changes, e.g. r0 is 1 and r1=r2=r3=0, then
ETAM++ =1+ 3=4.
3. If two bits change, e.g. r0 and r2 are 1 and r1=r3=0, then
ETAM++=6+4*d02. There are two subcases:
A. The 2 bits change in the same direction i.e.
d02=0 and ETAM++=6.
B. The 2 bits change in the opposite direction
i.e. d02=1 and ETAM++=10
4. If 3 bits change, e.g. r0, r2 and r3 are 1 and r1=0, then
ETAM++=6+4*(d02+d03+d23)
There are two subcases:
A. All 3 bits change in the same direction i.e.
d02+d03+d23=0, then ETAM++=6.
B. One bit changes in the opposite direction e.g.
d03=1, d23=1 and d02=0, then ETAM++=10.
5. If all 4 bits change,
ETAM++=4+4*(d01+d02+d03+d12+d13+d23)
There are three subcases:
A. All 4 bits change in the same direction i.e. all
dij=0, then ETAM++=4
B. One bit changes in the opposite direction
compared with
ETAM++=16.
C. Two bits change in the opposite direction with
respect to the other two, then ETAM++=20.
Figure 3 illustrates all possible cases as described above. It
should be clear from the above discussion that when bits
change in opposite directions there is higher ETAM++
value generated. This has a physical explanation: the
voltage difference between such lines is double the voltage
of one line changing and the other remaining constant,
therefore the power consumed on the resistances due to this
voltage difference is quadrupled.
i.e. ri=0
∀i, then
the other 3, then
(20)BB
BBBBBBBB
BBBBBBBB
BBBBBBBB
BBBBBB
V
2
−
C
P
DD
}
{
21
33
1
22
21
33
1
11
21
22
1
1
−
1
21
3
−
3
1
0
−
0
21
2
−
2
1
00
21
11
1
00
21
3
−
3
21
22
21
11
21
00
2
)](
)[()]()[()](
)[( )]()[()](
)[()]()[()(
)()()(
*
−
−−−
−−−
−−−
−−
−+−−−+−
−−+−−−+−
−−+−−−+−
+−+−+−=
(22) d*4rr
=
BBBB and
⊕
(21)
−
B
−
BBBr
ijjijjii
iiiii
+−
−
−−
21
211
)]
)(
(23) BBBBBBBB d
1
j
j
1
i
i
1
j
j
1
i
i
ij
?
=
(25) d
+
d
+
d
+
d d d rrrrrr
rrrrrrrrrr ETAM
}
)
2313120302
(*4
01323121
30201
+++⊕+⊕+⊕
+⊕+⊕+
(24)
d
+
d
+
d
+
d d d rrrr
rrrrrrrrrrrr
V
2
C
P
}
)
2313120302
DD
{
( *4
*
013231
213020103210
2
+++⊕+⊕
+⊕+⊕+⊕+⊕++++=