Interconnection networks in Systems-On-Chip begin to have a non-negligible impact on the power consumption of a whole system. This is because of increasing inter-wire capacitances that are in the same order of magnitude as intrinsic capacitances as far as deep-submicron designs are concerned. This trend has been recognized in recent research work. In this work, we present a physical model that takes into account inter-wire capacitances. Subsequently we propose a novel encoding scheme based on this physical model and targeted for address buses. We demonstrate that our encoding method improves power consumption by up to 62.5% and thus is exceeding all current approaches including our own previous one. In addition, the hardware of the bus encoding/decoding interfaces is compact to implement. We have conducted extensive simulations using SOC applications like, for example, an MPEGII encoder to evaluate the advantages of our approach.
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"Due to crosstalk noise, the coupling effect not only aggravates the powerdelay metrics but also deteriorates the signal integrity. Many techniques have been developed to reduce the coupling capacitance effect using bus encoding schemes         . Bus encoding is an elegant and effective technique for eliminating the crosstalk effect, and provides a reliability bound for onchip interconnects. "
[Show abstract][Hide abstract] ABSTRACT: Energy-efficient and reliable channels are provided for on-chip interconnection networks (OCINs) using a self-calibrated voltage scaling technique with self-corrected green (SCG) coding scheme. This self-calibrated low-power coding and voltage scaling technique increases reliability and reduces energy consumption simultaneously. The SCG coding is a joint bus and error correction coding scheme that provides a reliable mechanism for channels. In addition, it achieves a significant reduction in energy consumption via a joint triplication bus power model for crosstalk avoidance. Based on SCG coding scheme, the proposed self-calibrated voltage scaling technique adjusts voltage swing for energy reduction. Furthermore, this technique tolerates timing variations. Based on UMC 65 nm CMOS technology, the proposed channels reduces energy consumption by nearly 28.3% compared with that for uncoded channels at the lowest voltage. This approach makes the channels of OCINs tolerant of transient malfunctions and realizes energy efficiency.
Journal of Electrical and Computer Engineering 01/2012; 2012. DOI:10.1155/2012/697039
"2) Bus Encoding: One common technique used to minimize power consumption on busses, is the choice of appropriate encoding schemes that reduce the switching activity without affecting the signal information content , . This approach has been extended to account for interwire capacitances ,  and reliability issues , . Bus encoding techniques have shown effectiveness in reducing power consumption, although the best results are generally achieved in specific environments such as address busses. "
[Show abstract][Hide abstract] ABSTRACT: Systems-on-Chip (SoC) design involves several challenges, stemming from the extreme miniaturization of the physical features and from the large number of devices and wires on a chip. Since most SoCs are used within embedded systems, specific concerns are increasingly related to correct, reliable, and robust operation. We believe that in the future most SoCs will be assembled by using large-scale macro-cells and interconnected by means of on-chip networks. We examine some physical properties of on-chip interconnect busses, with the goal of achieving fast, reliable, and low-energy communication. These objectives are reached by dynamically scaling down the voltage swing, while ensuring data integrity-in spite of the decreased signal to noise ratio-by means of encoding and retransmission schemes. In particular, we describe a closed-loop voltage swing controller that samples the error retransmission rate to determine the operational voltage swing. We present a control policy which achieves our goals with minimal complexity; such simplicity is demonstrated by implementing the policy in a synthesizable controller. Such a controller is an embodiment of a self-calibrating circuit that compensates for significant manufacturing parameter deviations and environmental variations. Experimental results show that energy savings amount up to 42%, while at the same time meeting performance requirements.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 02/2005; 13(1-13):126 - 139. DOI:10.1109/TVLSI.2004.834241 · 1.36 Impact Factor