An On-chip Communication Mechanism Design in the Embedded Heterogeneous Multi-core Architecture.
ABSTRACT Much attention is now placed on the CMP (chip multiprocessor) architecture design while one important issue in this domain is the on-chip communication mechanism. The classic design of communication mechanism in embedded heterogeneous multi-core processor only satisfies its basic communication requirement and will cost a lot of additional communication. This paper proposes a novel communication mechanism called 'Main-Cooperation' model whose kernel component controls all the on-chip communication. The experimentation result shows that our model is 23% better than the classic one in the domain.
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Conference Paper: A low power open multimedia application platform for 3G wireless[Show abstract] [Hide abstract]
ABSTRACT: This paper describes an SOC design of a complex, low power and high performance open multimedia application platform (OMAP<sup>TM</sup>) for 3G wireless. The design integrates a high performance DSP subsystem based on a low power TMS320C55x DSP and an MPU subsystem based on the ARM9 microprocessor for the optimal combination of high performance with low power consumption. This paper explains the system design and the SoC implementations of the platform.SOC Conference, 2003. Proceedings. IEEE International [Systems-on-Chip]; 10/2003
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ABSTRACT: Describes how multimedia applications will be enabled in 3G wireless terminals thanks to the efficiency of the DSP core embedded in the TI Open Multimedia Application Platform (OMAP). The OMAP H/W architecture is described, with an emphasis on how multimedia applications (video, audio, speech) will benefit from this advanced architecture. The paper also depicts the advantages provided by a combined RISC/DSP architecture, compared to a single RISC architecture, for 3G multimedia mobile applicationsAcoustics, Speech, and Signal Processing, 2001. Proceedings. (ICASSP '01). 2001 IEEE International Conference on; 02/2001
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ABSTRACT: Helper threading is a technique that utilizes a second core or logical processor in a multi-threaded system to improve the performance of the main thread. A helper thread executes in parallel with the main thread that it attempts to accelerate. In this paper, the helper thread merely prefetches data into a shared cache and does not incur any other programmer visible effects. Helper thread prefetching has been proposed as a viable solution in various scenarios where it is difficult to prefetch efficiently within the main thread itself. This paper presents our helper threading experience on SUN's second dual-core SPARC microprocessor, the UltraSPARC IV+. The two cores on this processor share an on-chip L2 and an off-chip L3 cache. We present a compiler framework to automatically construct helper threads and evaluate our scheme on the UltraSPARC IV+ processor. Our preliminary results using helper threads on the SPEC CPU2000 suite show gains of up to 22% on programs that suffer substantial L2 cache misses while at the same time incurring negligible losses on programs that do not suffer L2 cache misses.Parallel Architectures and Compilation Techniques, 2005. PACT 2005. 14th International Conference on; 10/2005