Conference Paper

Towards Embedded Artificial Intelligence Based Security for Computer Systems.

Dept. of Comput. & Electron. Syst., Univ. of Essex, Colchester
DOI: 10.1109/BLISS.2008.13 Conference: 2008 ECSIS Symposium on Bio-inspired, Learning, and Intelligent Systems for Security, BLISS 2008, Edinburgh, UK, 4-6 August 2008
Source: DBLP

ABSTRACT This paper presents experiments using Artificial Intelligence (AI) algorithms for online monitoring of integrated computer systems, including System-on-Chip based embedded systems. This new framework introduces an AI-lead infrastructure that is intended to operate in parallel with conventional monitoring and diagnosis techniques. Specifically, an initial application is presented, where each of the systempsilas software tasks are characterised online during their execution by a combination of novel hardware monitoring circuits and background software. These characteristics then stimulate a Self-Organising Map based classifier which is used to detect abnormal system behaviour, as caused by failure and malicious tampering including viruses. The approach provides a system-level perspective and is shown to detect subtle anomalies.

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    ABSTRACT: This paper presents a system level framework for system-on-chip (SoC) based embedded devices that may include adaptive and reconfigurable elements. Current development support and debugging solutions are highly dependant on off-line post-mortem style inspection, and even those that utilise tracing for real-time and schedule-critical systems rely on external development tools and environments. This new framework introduces an AI-lead infrastructure that has the potential to reduce much of the development effort while complementing existing debugging circuits. Specifically this paper investigates how to use a Kohonen self-organising map (SOM) as a classifier, and shows a preliminary investigation into how to determine the quality of a map after training. This classifier is a first step in diagnosing failure, degradation and anomalies (i.e. provides condition monitoring) in an embedded system from a system level point of view, and in the larger task of self-diagnosis of an embedded system.
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    ABSTRACT: Monitoring circuitry is presented that extracts properties and features from a complex system based on a system-on-chip based device to support ICmetrics, a novel security concept that aims to uniquely identify and secure an embedded system based on its own behavioural identity. The circuits utilise a novel approach to profiling the instruction fetches and data accesses associated with each of the systempsilas component software tasks so that a representation of their address distributions can be generated online when required. By using profiling circuits with adaptive allocation of counters and by exploiting existing debugging infrastructure circuits, the overall resource requirement is kept sufficiently low for real-world applications. Experimental results are provided to illustrate the nature of features that can be obtained.
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    ABSTRACT: The introduction of complex systems-on-chip (SoC) devices with multiple processor cores presents new challenges for embedded systems developers. Novel development tools specifically targeting complex SoC will help overcome these challenges, but are typically limited by inadequate debug support facilities within the SoC. High-quality debug support with advanced features is essential to take full advantage of complex SoC devices in challenging applications while simultaneously reducing development time. Here, existing strategies for providing comprehensive SoC debug support targeting hard real-time applications, such as automotive control, where development challenges are overwhelming are reviewed. This overview includes an evaluation of the available solutions and their suitability for use with the next generation of complex SoC based on multiple processor cores. It is shown that many existing solutions do not readily permit developers to take advantage of the complex features integrated into the next generation of SoC. The essential features of debug support for multiple processor core SoCs are summarised and discussed. Recommendations are made for SoC designers and for the future direction of research in this area, with the aim of providing a more suitable foundation for new development tools. Such tools are badly needed for all hard real-time embedded systems and are paramount to managing the development complexity introduced by SoC devices with multiple highly interactive processor cores and active peripherals.
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