Conference Paper
A faster distributed arithmetic architecture for FPGAs.
DOI: 10.1145/503048.503054
Source: DBLP

Conference Paper: A novel FPGA logic block for improved arithmetic performance.
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ABSTRACT: To improve FPGA performance for arithmetic circuits, this paper proposes a new architecture for FPGA logic cells that includes a 6:2 compressor. The new cell features additional fast carrychains that concatenate adjacent compressors and can be routed locally without the global routing network. Unlike previous carrychains for binary and ternary addition, the carry chain used by the new cell only spans 2 logic blocks, which significantly improves the delay of multiinput addition operations mapped onto the FPGA. The delay and area overhead that arises from augmenting a traditional FPGA logic cell with the new compressor structure is minimal. Using this new cell, we observed an average speedup in combinational delay of 1.41 x compared to adder trees synthesized using ternary adders.Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, FPGA 2008, Monterey, California, USA, February 2426, 2008; 01/2008 
Conference Paper: AreaEfficient FIR Filter Design on FPGAs using Distributed Arithmetic
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ABSTRACT: In this paper, a highly areaefficient multiplierless FIR filter is presented. Distributed Arithmetic (DA) has been used to implement a bitserial scheme of a general asymmetric version of an FIR filter, taking optimal advantage of the 4input LUTbased structure of FPGAs. Furthermore, we have introduced a modification in the accumulator stage to achieve further savings. The proposed filter has been designed and synthesized with Altera Quartus II, and implemented on a Stratix FPGA device. Our results show reduced area requirements in comparison to previous LUTless DA architecturesSignal Processing and Information Technology, 2006 IEEE International Symposium on; 09/2006  [Show abstract] [Hide abstract]
ABSTRACT: To improve FPGA performance for arithmetic circuits that are dominated by multiinput addition operations, an FPGA logic block is proposed that can be configured as a 6:2 or 7:2 compressor. Compressors have been used successfully in the past to realize parallel multipliers in VLSI technology; however, the peculiar structure of FPGA logic blocks, coupled with the high cost of the routing network relative to ASIC technology, renders compressors ineffective when mapped onto the general logic of an FPGA. On the other hand, current FPGA logic cells have already been enhanced with carry chains to improve arithmetic functionality, for example, to realize fast ternary carrypropagate addition. The contribution of this article is a new FPGA logic cell that is specialized to help realize efficient compressor trees on FPGAs. The new FPGA logic cell has two variants that can respectively be configured as a 6:2 or a 7:2 compressor using additional carry chains that, coupled with lookup tables, provide the necessary functionality. Experiments show that the use of these modified logic cells significantly reduces the delay of compressor trees synthesized on FPGAs compared to stateoftheart synthesis techniques, with a moderate increase in area and power consumption.TRETS. 01/2009; 2.
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