Conference Paper

# A faster distributed arithmetic architecture for FPGAs.

DOI: 10.1145/503048.503054 Conference: the 2002 ACM/SIGDA tenth international symposium

Source: DBLP

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**ABSTRACT:**In this paper, we present a comparison between two methods, the modified Loeffler algorithm (11 MUL and 29 ADD) and Distributed Arithmetic, to implement the DCT/IDCT algorithm for MPEG or H.26x video compression using VHDL description language. The implementation has been achieved on Altera Stratix EP1S10 FPGA which provides a dedicated DSP blocks required for common signal processing functions. A new solution based on this DSP blocks used for to implement multipliers for the modified Loeffler algorithm in order to optimize speed and area.01/2006; -
##### Conference Paper: Area-Efficient FIR Filter Design on FPGAs using Distributed Arithmetic

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**ABSTRACT:**In this paper, a highly area-efficient multiplier-less FIR filter is presented. Distributed Arithmetic (DA) has been used to implement a bit-serial scheme of a general asymmetric version of an FIR filter, taking optimal advantage of the 4-input LUT-based structure of FPGAs. Furthermore, we have introduced a modification in the accumulator stage to achieve further savings. The proposed filter has been designed and synthesized with Altera Quartus II, and implemented on a Stratix FPGA device. Our results show reduced area requirements in comparison to previous LUT-less DA architecturesSignal Processing and Information Technology, 2006 IEEE International Symposium on; 09/2006 -
##### Article: Energy Scalable Distributed Arithmetic on a Field Programmable Gate Array and a Standard-Cell Core

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**ABSTRACT:**Abstract In today’s proactive computing age, sensor networks monitor the environ- ment, collect data, and execute tasks that aect our lives. The main ingredient to this process is a tiny sensor node that demands a long operating lifetime. Because of the sluggish growth of battery energy density, several research groups have developed technologies to power these sensors with scavenged energy from vibration and light. This highly variable supply mandates precision-on-demand processing. Distributed Arithmetic (DA), a bit-serial algorithm for dot product computation, possesses this capability to trade output quality for power consumption as demonstrated with the use of full-custom circuits. This thesis evaluates the energy scalability of a DA-based low-pass lter on a modern eld programmable gate array (FPGA) and a standard-

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