Rate analysis for streaming applications with on-chip buffer constraints.
ABSTRACT While mapping a streaming (such as multimedia or network packet processing) application onto a specified architecture, an important issue is to determine the input stream rates that can be supported by the architecture for any given mapping. This is subject to typical constraints such as on-chip buffers should not overflow, and specified play out buffers (which feed audio or video devices) should not underflow, so that the quality of the audio/video output is maintained. The main difficulty in this problem arises from the high variability in execution times of stream processing algorithms, coupled with the bursty nature of the streams to be processed. We present a mathematical framework for such a rate analysis for streaming applications, and illustrate its feasibility through a detailed case study of a MPEG-2 decoder application. When integrated into a tool for automated design-space exploration, such an analysis can be used for fast performance evaluation of different stream processing architectures.
- SourceAvailable from: psu.eduACM Trans. Design Autom. Electr. Syst. 01/2006; 11:564-592.
Conference Proceeding: Video Quality Driven Buffer Sizing via Frame Drops[show abstract] [hide abstract]
ABSTRACT: We study the impact of video frame drops in buffer constrained multiprocessor system-on-chip (MPSoC) platforms. Since on-chip buffer memory occupies a significant amount of silicon area, accurate buffer sizing has attracted a lot of research interest lately. However, all previous work studied this problem with the underlying assumption that no video frame drops can be tolerated. In reality, multimedia applications can often tolerate some frame drops without significantly deteriorating their output quality. Although system simulations can be used to perform video quality driven buffer sizing, they are time consuming. In this paper, we first demonstrate a dual-buffer management scheme to drop only the less significant frames. Based on this scheme, we then propose a formal framework to evaluate the buffer size vs. video quality trade-offs, which in turn will help a system designer to perform quality driven buffer sizing. In particular, we mathematically characterize the maximum numbers of frame drops for various buffer sizes and evaluate how they affect the worst-case PSNR value of the decoded video. We evaluate our proposed framework with anMPEG-2 decoder and compare the obtained results with that of a cycle-accurate simulator. Our evaluations show that for an acceptable quality of 30 dB, it is possible to reduce the buffer size by up to 28.6% which amounts to 25.88 megabits.Embedded and Real-Time Computing Systems and Applications (RTCSA), 2011 IEEE 17th International Conference on; 10/2011
Conference Proceeding: Generalized Rate Analysis for Media-Processing Platforms.[show abstract] [hide abstract]
ABSTRACT: In this paper we address the "rate analysis" problem for media-processing platforms consisting of multiple proces- sor cores connected in a pipelined fashion. More pre- cisely, we aim at determining tight bounds on the rates at which multimedia streams can be fed into such architec- tures. These bounds depend on architectural constraints (e.g. the available on-chip memory, bus arbitration policies, etc.), as well as the application characteristics (e.g. appli- cation partitioning and mapping, workload rates generated by different tasks, etc.). The proposed framework for rate analysis can be used for fast design space exploration to determine how these bounds change with different architec- tural parameters, mapping of the application, or changing the QoS requirements associated with the input streams.12th IEEE Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2006), 16-18 August 2006, Sydney, Australia; 01/2006