Parallel cross-layer optimization of high-level synthesis and physical design.

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Outline Motivation Poposed Work Results Summary
Parallel Cross-Layer Optimization of High-Level
Synthesis and Physical Design
James Williamson, Li Shang (University of Colorado, Boulder)
Yinghai Lu, Hai Zhou (Northwestern University)
Xuan Zeng (Fudan University)
January 27, 2011

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Outline Motivation Poposed Work Results Summary
Outline
Motivation
Problem Motivation
Previous Work
Goals and Contributions
Research Introduction
Poposed Work
Parallel Algorithm Flow
Mapping to Heterogeneous Architecture
Physcal Design on GPU
Results
Experimental Setup
GPU Floorplanner Results
Parallel Cross-Layer Optimization Results
Summary

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Outline Motivation Poposed Work Results Summary
Problem Introduction
Motivation ISCALP Research Goals Research Introduction
Modern VLSI Design Flow
? Modern VLSI design follows a top-down hierarchical flow
? Design abstraction decreases throughout the flow
? Design layers are addressed sequentially
? Each design layer guides the next

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Outline Motivation Poposed Work Results Summary
Problem Introduction
Motivation ISCALP Research Goals Research Introduction
The Design Closure Problem
? High-level abstractions can cause incorrect decision making
? Large portions of the design space are irreversibly pruned
? Errors found when physical information (interconnect, area)
becomes known, i.e. too late
? Entire design flow repetition is required to ensure design
closure – costly!
? The outlook is not good
? Growing transistor counts, technology scaling, etc. ensure
design closure will become increasingly difficult

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Outline Motivation Poposed Work Results Summary
Sequential Incremental Synthesis
Motivation ISCALP Research Goals Research Introduction
Incremental Floorplanning and High-Level Synthesis
? ISCALP, Zhong et al, 2002.
? Computes physical information to incrementally guide
high-level synthesis
? Iterative approach is better, but takes too long to compute
? True parallelism between layers not exposed