Conference Paper

On-line thermal aware dynamic voltage scaling for energy optimization with frequency/temperature dependency consideration

DOI: 10.1145/1629911.1630039 Conference: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009
Source: DBLP

ABSTRACT With new technologies, temperature has become a major issue to be considered at system level design. Without taking temperature aspects into consideration, no approach to energy or and performance optimization will be sufficiently accurate and efficient. In this paper we propose an on-line temperature aware dynamic voltage and frequency scaling (DVFS) technique which is able to exploit both static and dynamic slack. The approach implies an offline temperature aware optimization step and online voltage-frequency settings based on temperature sensor readings. Most importantly, the presented approach is aware of the frequency-temperature dependency, by which important additional energy savings are obtained.

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Available from: Zebo Peng, Sep 26, 2015
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    • "thermal-runaway, are more prone to the increasing gate density that facilitates the lateral heat flow between adjacent cores or functional blocks. Dynamic Thermal Management (DTM) techniques are proposed as a class of microarchitectural and/or OS-level strategies for runtime temperature control, where adjustment mechanisms including runtime thread migration [6]–[8] and DVFS [9]–[13] are applied. Whereas the abovementioned techniques focus on workload manipulation by deciding which speed level or mapped processor the task 1 runs at, the adaptive applications provide an orthogonal management perspective, where the flexibility in execution is able to tradeoff the heat generation. "
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    ABSTRACT: For applications featuring adaptive workloads, the quality of their task execution can be dynamically adjusted given the runtime constraints. When mapping them to heterogeneous MPSoCs, it is expected not only to achieve the highest possible execution quality, but also meet the critical thermal challenges from the continuously increasing chip density. Prior thermal management techniques, such as Dynamic Voltage/Frequency Scaling (DVFS) and thread migration, do not take into account the trade-off possibility between execution quality and temperature control. In this paper, we explore the capability of adaptive workloads for effective temperature control, while maximally ensuring the execution Quality-of-Service (QoS). We present a thermal-aware dynamic frequency scaling (DFS) algorithm on heterogeneous MPSoCs, where judicious frequency selection achieves QoS maximization under the temperature threshold, which is converted to the thermal-timing deadline as an additional execution constraint. Results show that our frequency scaling algorithm achieves as large as 31.5% execution cycle/QoS improvement under thermal constraints.
    Design, Automation, and Test in Europe; 03/2014
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    • "The increasing popularity of multi-core systems and the rising performance demand have made energy efficiency a critical design objective for system designers. Catalyzed by continuous transistor scaling, an exponential increase in transistor density for higher performance platforms has led to sharp rise in power/energy consumption [1], [2]. The continuously increased power consumption has resulted in soaring chip temperature, which adversely impacts the performance, reliability, and packaging/cooling costs [3]. "
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    ABSTRACT: Energy minimization is a critical issue and challenge when considering the cyclic dependency of leakage power and temperature as IC technology reaches deep sub-micron level. In this paper, we present an analytical method to calculate the energy consumption efficiently and effectively for a given voltage schedule on a multi-core platform, with the leakage/temperature dependency taken into consideration. Our experiments show that the proposed method can achieve a speedup of 15 times compared with the numerical method, with a relative error of no more than 1.5%.
    Low Power Electronics and Design (ISLPED), 2013 IEEE International Symposium on; 09/2013
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    • "In such a scenario, the off-line algorithms introduced above become useless. Bao et al. [1] proposed an on-line temperature aware DVS technique to minimize the energy consumption when scheduling a task graph. This approach requires extensive off-line static analysis to generate a lookup table (LUT) for each task under various starting temperature and time, so that the scheduler can adjust the processor speed accordingly to minimize energy consumption on-line. "
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    ABSTRACT: As the semiconductor technology proceeds into the deep sub-micron era, leakage and its dependency with the temperature become critical in dealing with the power/energy minimization problem. In this paper, we develop an analytical method to estimate energy consumption on-line with the leakage/temperature dependency taken into consideration. Based on this method, we develop an on-line scheduling algorithm to reduce the overall energy consumption for a hard real-time system scheduled according to the Earliest Deadline First (EDF) policy. Our experimental results show that the proposed energy estimation method can achieve up to 210X speedup compared with an existing approach while still maintaining high accuracy. In addition, with a large number of different test cases, the proposed energy saving scheduling method consistently outperforms two closely related researches in average by 10% and 14% respectively.
    01/2012; DOI:10.1109/ASPDAC.2012.6165042
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