Conference Paper

On-line thermal aware dynamic voltage scaling for energy optimization with frequency/temperature dependency consideration

DOI: 10.1145/1629911.1630039 Conference: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009
Source: DBLP


With new technologies, temperature has become a major issue to be considered at system level design. Without taking temperature aspects into consideration, no approach to energy or and performance optimization will be sufficiently accurate and efficient. In this paper we propose an on-line temperature aware dynamic voltage and frequency scaling (DVFS) technique which is able to exploit both static and dynamic slack. The approach implies an offline temperature aware optimization step and online voltage-frequency settings based on temperature sensor readings. Most importantly, the presented approach is aware of the frequency-temperature dependency, by which important additional energy savings are obtained.

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    • "thermal-runaway, are more prone to the increasing gate density that facilitates the lateral heat flow between adjacent cores or functional blocks. Dynamic Thermal Management (DTM) techniques are proposed as a class of microarchitectural and/or OS-level strategies for runtime temperature control, where adjustment mechanisms including runtime thread migration [6]–[8] and DVFS [9]–[13] are applied. Whereas the abovementioned techniques focus on workload manipulation by deciding which speed level or mapped processor the task 1 runs at, the adaptive applications provide an orthogonal management perspective, where the flexibility in execution is able to tradeoff the heat generation. "
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    ABSTRACT: For applications featuring adaptive workloads, the quality of their task execution can be dynamically adjusted given the runtime constraints. When mapping them to heterogeneous MPSoCs, it is expected not only to achieve the highest possible execution quality, but also meet the critical thermal challenges from the continuously increasing chip density. Prior thermal management techniques, such as Dynamic Voltage/Frequency Scaling (DVFS) and thread migration, do not take into account the trade-off possibility between execution quality and temperature control. In this paper, we explore the capability of adaptive workloads for effective temperature control, while maximally ensuring the execution Quality-of-Service (QoS). We present a thermal-aware dynamic frequency scaling (DFS) algorithm on heterogeneous MPSoCs, where judicious frequency selection achieves QoS maximization under the temperature threshold, which is converted to the thermal-timing deadline as an additional execution constraint. Results show that our frequency scaling algorithm achieves as large as 31.5% execution cycle/QoS improvement under thermal constraints.
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    • "Thermally aware approaches [2] [3] [4] take into account the chip operating temperatures while scaling the voltages while the others do not. It is to be noted that schemes in [2] and [3] do not deal with thermal cycles. The authors of [4] show the effect of thermal cycles on lifetime reliability, but do not put forward an online approach to voltage scaling taking into account the thermal cycles. "
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    ABSTRACT: Dynamic voltage and frequency scaling (DVFS) is heavily used for power management in real-time environments. Although the schemes leveraging DVFS provide significant power reduction, adverse effects on chip reliability are possible. Alternate increase and decrease in operating voltage and frequency leads to thermal cycling. Increasing transistor packing density leads to a larger range of possible operating temperatures, exacerbating the thermal cycling problem. Also, the chip reliability quantification process does not include and represent the effects of small scale thermal cycles. A good number of in-field chip failures are attributed to the consequences of these. Thus, it is imperative to include their effects into the processor voltage and frequency selection process. Our work develops an integrated processor thermal and performance management technique centered on novel polynomial time scheduling algorithms that lead to lowering of thermal cycles in soft real time environments. Our technique leverages application awareness and runtime monitoring for improving chip lifetime, while achieving considerable energy savings. We show that a significant reduction in thermal cycles and peaks is possible, leading to longer chip life expectations.
    ACM SIGOPS Operating Systems Review 11/2013; 47(3):10-17. DOI:10.1145/2553070.2553073
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    • "The increasing popularity of multi-core systems and the rising performance demand have made energy efficiency a critical design objective for system designers. Catalyzed by continuous transistor scaling, an exponential increase in transistor density for higher performance platforms has led to sharp rise in power/energy consumption [1], [2]. The continuously increased power consumption has resulted in soaring chip temperature, which adversely impacts the performance, reliability, and packaging/cooling costs [3]. "
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