Conference Paper

On-line thermal aware dynamic voltage scaling for energy optimization with frequency/temperature dependency consideration.

DOI: 10.1145/1629911.1630039 Conference: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009
Source: DBLP

ABSTRACT With new technologies, temperature has become a major issue to be considered at system level design. Without taking temperature aspects into consideration, no approach to energy or and performance optimization will be sufficiently accurate and efficient. In this paper we propose an on-line temperature aware dynamic voltage and frequency scaling (DVFS) technique which is able to exploit both static and dynamic slack. The approach implies an offline temperature aware optimization step and online voltage-frequency settings based on temperature sensor readings. Most importantly, the presented approach is aware of the frequency-temperature dependency, by which important additional energy savings are obtained.

  • [Show abstract] [Hide abstract]
    ABSTRACT: Enabled by high-speed networking in commercial, scientific, and government settings, the realm of high performance is burgeoning with greater amounts of computational and storage resources. Large-scale systems such as computational grids consume a significant amount of energy due to their massive sizes. The energy and cooling costs of such systems are often comparable to the procurement costs over a year period. In this survey, we will discuss allocation and scheduling algorithms, systems, and software for reducing power and energy dissipation of workflows on the target platforms of single processors, multicore processors, and distributed systems. Furthermore, recent research achievements will be investigated that deal with power and energy efficiency via different power management techniques and application scheduling algorithms. The article provides a comprehensive presentation of the architectural, software, and algorithmic issues for energy-aware scheduling of workflows on single, multicore, and parallel architectures. It also includes a systematic taxonomy of the algorithms developed in the literature based on the overall optimization goals and characteristics of applications.
    ACM Journal on Emerging Technologies in Computing Systems 01/2012; 8(4):1-37. · 0.76 Impact Factor
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: The benefits of combinatorial optimization techniques for the solution of real-world industrial problems are an acknowledged evidence; yet, the application of those approaches to many practical domains still encounters active resistance by practitioners, in large part due to the difficulty to come up with accurate declarative representations. We propose a simple and effective technique to bring hard-to-describe systems within the reach of Constraint Optimization methods; the goal is achieved by embedding into a combinatorial model a softcomputing paradigm, namely Neural Networks, properly trained before their insertion. The approach is flexible and easy to implement on top of available Constraint Solvers. To provide evidence for the viability of the proposed method, we tackle a thermal aware task allocation problem for a multi-core computing platform.
    Principles and Practice of Constraint Programming - CP 2011 - 17th International Conference, CP 2011, Perugia, Italy, September 12-16, 2011. Proceedings; 01/2011
  • [Show abstract] [Hide abstract]
    ABSTRACT: We present a design-for-test apparatus for measuring real-time, on-chip heat map images with high granularity. Our test chip implemented an 8 × 8 matrix of temperature sensors on-chip in a 0.18µm process with minimal area and power consumption overhead. We then implemented a test interface for measuring individual temperatures with an off-chip ADC and a custom FPGA-based microcontroller with serial UART and ethernet capabilities. This apparatus was used to animate the variation in temperature across the die over time. While temperature sensors have been integrated extensively in VLSI circuits, a single sensor cannot take accurate measurements across an entire chip. Infrared cameras are excellent for direct measurement of temperature across a die, however with new, so-called 3D integrated circuit technology, an infrared camera cannot measure the temperature inside a three dimensional stack. Since performance, reliability, and power consumption are all related to temperature, operating constraints for temperature must be verified to ensure proper device operation. Our design-for-test apparatus demonstrates that fine-grain, real-time measurements of temperature on-chip can be accomplished in real-time with less than 0.5% area overhead in a 1.5 × 1.5mm2 total core area, and less than 1mW power consumption added to the device under test (DUT).

Full-text (2 Sources)

Available from
Jun 3, 2014