Conference Paper

Thermal Characterization and Thermal Management in Processor-Based Systems.

Departamento de Ingeniería Electrónica, Universidad Politécnica de Madrid, 28040, Madrid, Spain; Department of Telecommunication Services and Usage, INSA Albert Einstein, 69621, Villeurbanne Cedex, France; Dpt. of Computer Architecture and Systems Prof, Complutense University of Madrid, 28040, Madrid, Spain
Conference: Power-aware Computing Systems, 21.01. - 26.01.2007
Source: DBLP

ABSTRACT The register file is one of the hottest devices in processor-based systems. Leakage reduction techniques and DTM mechanisms require a thermal characterization of the hardware. This paper presents a thermal model to analyze the temperature evolution in the shared register files found on VLIW systems. The use of this model allows the analysis of several factors that have an strong impact on the heat transfer. The results obtained can be used in the design of temperature-aware compilers and place&route tools. @InProceedings{ayala_et_al:DSP:2007:1110, author = {Jos{'e} Luis Ayala and Anya Apavatjrut and David Atienza and Marisa L{'o}pez-Vallejo and Carlos A. L{'o}pez-Barrio}, title = {Thermal Characterization and Thermal Management in Processor-Based Systems}, booktitle = {Power-aware Computing Systems}, year = {2007}, editor = {Luca Benini and Naehyuck Chang and Ulrich Kremer and Christian W. Probst}, number = {07041}, series = {Dagstuhl Seminar Proceedings}, ISSN = {1862-4405}, publisher = {Internationales Begegnungs- und Forschungszentrum f{"u}r Informatik (IBFI), Schloss Dagstuhl, Germany}, address = {Dagstuhl, Germany}, URL = {http://drops.dagstuhl.de/opus/volltexte/2007/1110}, annote = {Keywords: Thermal characterization, thermal model, register file} }

1 Bookmark
 · 
66 Views
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: The doubling of microprocessor performance every three years has been the result of two factors: more transistors per chip and superlinear scaling of the processor clock with technology generation. Our results show that, due to both diminishing improvements in clock rates and poor wire scaling as semiconductor devices shrink, the achievable performance growth of conventional microarchitectures will slow substantially. In this paper, we describe technology-driven models for wire capacitance, wire delay, and microarchitectural component delay. Using the results of these models, we measure the simulated performance---estimating both clock rate and IPC--- of an aggressive out-of-order microarchitecture as it is scaled from a 250nm technology to a 35nm technology. We perform this analysis for three clock scaling targets and two microarchitecture scaling strategies: pipeline scaling and capacity scaling. We find that no scaling strategy permits annual performance improvements of better than 12.5%, which is far worse than the annual 50-60% to which we have grown accustomed. 1
    10/2001;
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: Physical phenomena such as temperature have an increasingly important role in performance and reliability of modern process technologies. This trend will only strengthen with future generations. Attempts to minimize the design effort required for reaching closure in reliability and performance constraints are agreeing on the fact that higher levels of design abstractions need to be made aware of lower level physical phenomena. In this paper, we investigated techniques to incorporate temperature-awareness into high-level synthesis. Specifically, we developed two temperature-aware resource allocation and binding algorithms that aim to minimize the maximum temperature that can be reached by a resource in a design. Such a control scheme will have an impact on the prevention of hot spots, which in turn is one of the major hurdles in front of reliability for future integrated circuits. Our algorithms are able to reduce the maximum attained temperature by any module in a design by up to 19.6°C compared to a binding that optimizes switching power.
    Design Automation Conference, 2005. Proceedings. 42nd; 07/2005
  • [Show abstract] [Hide abstract]
    ABSTRACT: In this paper, we study leakage power reduction using power gating in the form of the virtual power/ground rails clamp (VRC) and multi-threshold CMOS (MTCMOS) techniques. We apply power gating to two circuit types: memory-based units and datapath components. Using a microarchitecture-level power simulator, as well as power and timing models derived from detailed circuit designs, we further study leakage power modeling and reduction at the system level for modern high-performance VLIW processors. We show that the leakage power can be over 40% of the total power for such processors. Moreover, we propose time-out scheduling of the VRC to reduce power up to 85.65% for an L2 cache. This power saving results in close to 1/3 of the total power dissipation for the VLIW processors we studied.
    Computer Aided Design, 2002. ICCAD 2002. IEEE/ACM International Conference on; 12/2002

Full-text (5 Sources)

View
56 Downloads
Available from
May 28, 2014