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Thermal Characterization and Thermal

Management in Processor-Based Systems⋆

Jos´ e L. Ayala1, Anya Apavatjrut2, David Atienza3, Marisa L´ opez-Vallejo1and

Carlos A. L´ opez-Barrio1

1Universidad Polit´ ecnica de Madrid, Departamento de Ingenier´ ıa Electr´ onica

Ciudad Universitaria s/n, 28040 Madrid, Spain

{jayala, marisa, barrio}@die.upm.es

2Department of Telecommunication Services and Usage, INSA

Albert Einstein, 69621 Villeurbanne Cedex, France

anya.apavatjrut@insa-lyon.fr

3Complutense University of Madrid, Dpt. of Computer Architecture and Systems

Prof. Jos´ e Garc´ ıa Santesmases s/n, 28040 Madrid, Spain

datienza@dacya.ucm.es

Abstract. The register file is one of the hottest devices in processor-

based systems. Leakage reduction techniques and DTM mechanisms re-

quire a thermal characterization of the hardware. This paper presents a

thermal model to analyze the temperature evolution in the shared reg-

ister files found on VLIW systems. The use of this model allows the

analysis of several factors that have an strong impact on the heat trans-

fer. The results obtained can be used in the design of temperature-aware

compilers and place&route tools.

Keywords. Thermal characterization, thermal model, register file.

1 Introduction

The doubling of microprocessor performance every 18 months can be explained

by two facts: more transistors integrated per chip and superlinear scaling of the

processor clock with technology generation [1]. However, as CMOS technology

is scaled into the sub-100 nm region, the power density of microlectronic designs

increases steadily. For example, the power density of high performance micro-

processors is found to be 50W/cm2for the 100nm technology, while reaches the

100W/cm2for the 50nm technology [2]. This trend is becoming a key limiting

factor to the performance of current state-of-the-art microprocessors due to the

increase of the average temperature of the chip and the local hot spots.

System performance is affected for both temperature and supply voltage. As

is widely known, power consumption includes dynamic and leakage power. Leak-

age power consumption grows significantly as technology scales down because of:

⋆This work is partially supported by the Spanish Government Research Grant

TEC2006-00739

Dagstuhl Seminar Proceedings 07041

Power-aware Computing Systems

http://drops.dagstuhl.de/opus/volltexte/2007/1110

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L´ opez-Barrio

J. L. Ayala, A. Apavatjrut, D. Atienza, M. L´ opez-Vallejo, C. A.

increase of device leakage current due to reduction in threshold voltage, channel

length, and gate oxide thickness [3]; and the increasing number of idle modules

in a highly integrated system.

Moreover, the reliability of electronic devices is well known to exponentially

depend on the operation temperature due to the acceleration of several failure

mechanisms on hotter environments [4]. Even small differences in the operat-

ing temperature (10-15 C) can result in a 2x difference in the lifespan of the

devices [5]. Additionally, the higher operating temperature, the more aggres-

sive the cooling solution must be, which will lead to further increase in power

consumption [6].

From above, it can be seen how important is to estimate temperature at

different design stages, especially in the very early stages of the design flow.

The estimated temperature can be used to perform power, performance, and

reliability analysis, together with placement, packaging design, etc. As a result,

all the decisions use temperature as a guideline and the design is intrinsically

thermally optimized and free from thermal limitations.

Existing power simulators [7] calculate leakage power by assuming a fixed ra-

tio between dynamic and leakage power. This assumption is not accurate because

dynamic power and leakage power scale differently as a function of Vdd and tem-

perature. Furthermore, leakage power is sensitive to temperature while dynamic

power is independent of temperature. High-level leakage power modeling has

been studied. Several references [8] present high-level leakage power models with-

out temperature scaling. Therefore, none of these models is sufficient to study

microarchitecture-level power and temperature interaction. Microarchitecture-

level thermal modeling has also been studied. Brooks and Martonosi [9] model

the on-chip temperature as the average power consumption within a fixed time

window. [10] proposes a simple thermal calculation, applying a one-segment

lumped thermal resistance and capacitance circuit to model the entire chip and

package. HotSpot [11] provides a detailed thermal model based on an equivalent

distributed circuit of resistances and capacitances. However, this model do not

consider the temperature and voltage dependence of leakage power.

It is known that the register file is the hottest block in a modern micropro-

cessor chip [12]. Some DTM methods specifically targeted toward temperature

control in the register file were presented in [13] and [14]. Therefore, the ther-

mal characterization of this device, and the effect on temperature of high-level

factors, is needed.

This paper presents some current work on the thermal characterization of

the register file of VLIW architectures. Our work proposes a thermal model to

estimate the evolution in time of the temperature and analyzes some factor that

influence this heat distribution.

2 Thermal Model

For the development of the thermal model, a well known analogy between the

electrical circuits and the thermal sources is exploited. The silicon die and heat

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Thermal Characterization and Thermal Management3

spreader is composed in elementary cells in a cubic shape. The temperature for

every cell is computed using an RC model. The size of the cell trades-off the

simulation speed with the thermal accuracy.

Each cell is associated with a thermal capacitance and five thermal resis-

tances. Four resistances are used to model the horizontal thermal spreading,

whereas the fifth is used to model the vertical thermal behavior. The thermal

conductivity (horizontal and vertical) and capacitance, respectively, of each ele-

mentary cell are computed as follows:

Ghor= KG(Si/Cu)×

?h × w

?l × w

l

?

?

Gver= KG(Si/Cu)×

h

C = KC(Si/Cu)× l × h × w

where KG(Si/Cu)(thermal conductivity for silicon or copper), KC(Si/Cu)(ther-

mal capacitance per volume unit for silicon or copper), l (cell length), w (cell

width), h (cell height).

With this RC characterization, every cell is connected with the cells in the

surroundings. The heat dissipation of each block is modeled as a source connected

to the current node. A thermal circuit, which is similar to an electrical circuit, is

created and can be solved by a node voltage analysis. As a result, the temperature

of each block is obtained.

2.1 Register File Modeling

As was mentioned before, one of the goals of this work is to increase the model

granularity by focusing the analysis on the temperature behavior of the registers

inside the register file. To accomplish such goal, the register file is supposed to

be represented as a N × M matrix and every register belongs to one of the

elementary cells. Therefore, the thermal resistance and capacitance (R and C)

for every elementary cell and every specific floorplan, have to be calculated.

Elementary resistances calculation Since the total resistance and total ca-

pacitance of the device is known in advance, the register file can be decomposed

into smaller units. Each unit is associated with its own resistance and capaci-

tance as shown in Figure1.

From Figure 1, the total resistance for a cell is

Rcell= R +R

3=4R

3

Now, from Figure 3, the circuit can be decomposed in a matrix of N rows

by M columns of registers, and the resistance of every row can be calculated as

follows.

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L´ opez-Barrio

J. L. Ayala, A. Apavatjrut, D. Atienza, M. L´ opez-Vallejo, C. A.

Bottom

EW

S

Top

N

h

w

l

Fig.1. Equivalent RC circuit of a cell.

Fig.2. Resistances of the register unit.

Rcell,M=

?

?

(Rcell,M−1+ R)||R

2

?

+ R

=

(Rcell,M−1+ R) ×R

Rcell,M−1+3R

2

2

?

+ R

Supposing that Rcell,M−1= SM−1R and Rcell,M= SMR, then

SM=

??SM−1+ 1

SM−1+ 1.5

?

× 0.5

?

+ 1

Considering that each row is parallel with the others, the total resistance for

the device can be calculated dividing by the number of rows.

Rtot=Rcell,M

N

The resistance of each register can be computed as

R =NRtot

SM

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Thermal Characterization and Thermal Management5

Fig.3. Equivalent resistance circuit in a 2D map.

Elementary capacitances calculation The total capacitance of the circuit

can be calculated by considering each elementary capacitance to be parallel with

the others (see Figure 4).

The total capacitance can be computed for N rows and M columns in parallel

as

Ctot= C × N × M

The capacitance of every register can be computed as

C =

Ctot

N × M

Once the resistance and capacitance for each elementary cell are known, the

size of the elementary cell can be calculated supposing that it is a quadratic

cube by the expression

size =

R

KG(Si/Cu)

These last expressions are integrated in the VLSI simulator in order to re-

trieve the thermal behavior for every register in the register file for different

placements and topologies.

From [15], we employ the same expression to compute the temperature evo-

lution once the technology factors are calculated and the activities are obtained

by the simulator.

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L´ opez-Barrio

J. L. Ayala, A. Apavatjrut, D. Atienza, M. L´ opez-Vallejo, C. A.

Fig.4. Equivalent capacitance circuit.

Fig.5. Configuration files

Tc(n + 1) × 236= Tc(n) + ((cap × EC × 262) × act) +

+((A × 226− B × 226× (Tc(n)) ×

×(Tn(n) × 236− Tc(n) × 236)))/(226)

where Tc(n) is the temperature at step n, Tc(n + 1) is the temperature at step

n + 1, Tn(n) is the neighbor cell temperature, cap × EC is the temperature

difference due to the activities, act is the activity factor, A is the linear coefficient

and B is the quadratic one.

3 Experimental Results

Once the thermal model for the register file has been developed, it has been

integrated in the functional and thermal simulator of the VLIW system. In

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Fig.6. Thermal map for a condensed access pattern.

order to perform the thermal simulation of the system, an specific layout of the

architecture has to be designed.

The baseline architecture devised for the set of experiments resembles a com-

mon VLIW system with four processing cores, a shared memory subsystem, a

shared register file and a communication network. The layout of the system is

configured in a text file where the placement and size of these modules is coded

with letters (see Figure 5).

Before starting the simulation, the thermal parameters (the heat transfer

coefficient and the thermal conductivity for silicon and copper) must be set.

Also, the floorplan must be loaded.

During the simulation, the thermal coefficients and power coefficients for each

cell are computed. Since every cell is surrounded by other cells, a heat distribu-

tion from hotter cells to colder cells takes place. At the end of the simulation,

temperatures of all the cells are stored in a file.

The set of experiments we present here analyzes the effect of the access

pattern on the temperature of the register file. This analysis will allow to define

temperature-aware access policies that reduce the temperature of the device as

well as the power consumption [16]. These experiments have been performed for

every placement of the layout (positions 1, 2, 3 and 4) and three different access

patterns (registers accessed from a bank placed on the right hand side of the

register file, accessed registers randomly placed in several spots of the device

and registers accessed in an homogeneous manner as a chess board).

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L´ opez-Barrio

J. L. Ayala, A. Apavatjrut, D. Atienza, M. L´ opez-Vallejo, C. A.

Fig.7. Thermal map for a random access pattern.

The following graphs show the results for the three different accesses when

the register file is placed in position 4.

Figure 6 shows the evolution in time of the thermal map for the register file

when the registers are accessed from a bank located at the right hand side of

the device. As can be seen, the bank where the registers are accessed from is

increasingly heated as time advances. At the end, a large hot spot appears in

the register file, what can severely damage the device.

Figure 7 shows the evolution in time of the thermal map for the register file

when the registers are randomly accessed from several spots in the device. As

can be seen, these spots where the registers are accessed from are increasingly

heated as time advances. At the end, several hot spots appear on the register file

surface increasing the probability of chip damage. Therefore, an access pattern

what homogenizes the thermal map on the silicon surface must be found.

Figure 8 shows the evolution in time of the thermal map for the register file

when the registers are accessed in a “chess board” manner. As can be seen, this

access pattern homogenizes the temperature on the silicon because the accesses

are distributed across a larger surface. Moreover, the probability of hotspots is

minimized and the reliability of the system is not compromised.

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Thermal Characterization and Thermal Management9

Fig.8. Thermal maps for a “chess board” access pattern.

4 Conclusions

Leakage reduction and thermal management is one of the key issues in current

architectures. The proposed methodologies that optimize these metrics require

a thermal and accurate characterization of the hardware modules.

This paper has presented an efficient analytical model to analyze the tem-

perature evolution in the register file of a VLIW architecture, one of the hottest

devices of these systems. Moreover, we have also evaluated some of the factors

that can modify this thermal map.

The results obtained can be used in the design of temperature-aware com-

pilers and place&route tools.

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Thermal analysis of the shared