Conference Paper

RAM: Rapid Alignment Method.

DOI: 10.1007/978-3-642-27257-8_17 Conference: Smart Card Research and Advanced Applications - 10th IFIP WG 8.8/11.2 International Conference, CARDIS 2011, Leuven, Belgium, September 14-16, 2011, Revised Selected Papers
Source: DBLP

ABSTRACT Several countermeasures against side-channel analysis result in misalignment of power traces, in order to make DPA more difficult. In this paper we propose a new algorithm to align the measurements after this desynchronizing through the variations of the internal clock, random delays, etc. The algorithm is based on the ideas of SIFT and U-SURF algorithm that were originally proposed for image recognition. The comparison with other known methods favors our solution in terms of efficiency and computational complexity.

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    ABSTRACT: We suggest, in a methodological manner, the use of Wavelet transforms to improve side channel analysis (SCA). The proposed applications are involved in several side channel analysis aspects: storage of traces, patterns detection and noise filtering. We show that all these aspects are useful to improve evaluation of information leakages from embedded devices. In particular, we show how wavelets favour practical secret key recovery.
    Microarchitecture Workshops (MICROW), 2012 45th Annual IEEE/ACM International Symposium on; 01/2012
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    ABSTRACT: Generating random delays in embedded software is a common countermeasure to complicate side channel attacks. The idea is to insert dummy operations with varying lengths at different moments in time. This creates a non-predictable offset of the attacking point in the time dimension. Since the success of, e.g., a correlation power analysis (CPA) attack is largely affected by the alignment of the power traces, the adversary is forced to apply additional large computations or to record a huge amount of power traces to achieve acceptable results. In this paper, we present a new efficient method to identify random delays in power measurements. Our approach does not depend on how the random delays are generated. Plain uniform delays can be removed as well as Benoit-Tunstall [11] or improved floating mean delays [4]. The procedure can be divided into three steps. The first step is to convert the power trace into a string depending on the Hamming weights of the opcodes. After this, the patterns of the dummy operations are identified. The last step is to use a string matching algorithm to find these patterns and to align the power traces. We have started our analysis with two microcontrollers, an Atmel AVR ATmega8 and a Microchip PIC16F54. For our practical evaluation, we have focused on the ATmega8. However, the results can be applied to many other microcontrollers with a similar architecture.
    Proceedings of the 14th international conference on Information Security and Cryptology; 11/2011
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    ABSTRACT: This paper introduces a generic and automated methodology to protect hardware designs from side-channel attacks in a manner that is fully compatible with commercial standard cell design flows. The paper describes a tool that artificially adds jitter to the clocks of the sequential elements of a cryptographic unit, which increases the non-determinism of signal timing, thereby making the physical device more difficult to attack. Timing constraints are then specified to commercial EDA tools, which restore the circuit functionality and efficiency while preserving the introduced randomness. The protection scheme is applied to an AES-128 hardware implementation that is synthesized using both ASIC and FPGA design flows.
    Design, Automation Test in Europe Conference Exhibition (DATE), 2013; 01/2013

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